Monitoring of Gate Leakage Current on SiC Power MOSFETs: An Estimation Method for Smart Gate Drivers

Weckbrodt, Julien; Ginot, Nicolas; Batard, Christophe; Azzopardi, Stéphane

doi:10.1109/tpel.2021.3056648

Cited by 18 publications

(8 citation statements)

References 22 publications

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“…Compared with the method using anti‐parallel SBD, this method has smaller loop stray parameters [22]. Due to the unique carrier characteristics of BJT, certain pass‐through power consumption will be generated if the two push–pull circuits are directly short‐circuited, but the inducement of this pass‐through is essentially different from that of CMOS push–pull circuit.…”

Section: Amplification Circuitmentioning

confidence: 99%

“…In addition, the input signals in the existing applications are all provided by external devices instead of digital chips, and signal waveforms usually need to be modulated, which affects the performance of isolated drivers in actual HT environments in terms of volume, device selection and so on. In [22], the leakage current monitor technology can help to assist the gate driver work in harsh environment. In [23], gate driver integration technology has been introduced.…”

Section: Introductionmentioning

confidence: 99%

“…Si discrete device has much smaller leakage current than transistor in IC under the same voltage as a result of its larger volume and better HT resistance thanks to its lower thermal impedance. These features make Si discrete device another good choice for HT isolated gate driver under current conditions [10][11][12][13][14][15][16][17][18][19][20][21][22][23]. In [16] and [17], the conventional magnetic coupling isolation method is applied.…”

Section: Introductionmentioning

confidence: 99%

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Design and experiments of isolated gate driver using discrete devices for silicon carbide MOSFET

Jiang

Wang

et al. 2022

IET Power Electronics

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The high temperature (HT) characteristics of silicon carbide (SiC) devices enable power electronic converters to operate at higher ambient temperature, and the importance of HT isolated gate drivers is becoming increasingly significant. Compared with the complex silicon on insulator (SOI) HT chips and normal silicon (Si) ICs, the Si‐based discrete devices can well balance the temperature capability and design cost. A feasible isolated gate driver design method is proposed in this paper by using discrete MOSFETs, discrete BJTs and other passive components with consideration of cost and can be with less leakage current than normal integrated circuits. The function of gate driver includes signal isolation and signal amplification. In the signal isolation part, a CMOS‐based isolation circuit is proposed with its merits. In the signal amplification part, normal topologies are improved to get better efficiency and high‐speed capability. SiC power module‐based double pulse test is used to verify the switching performance, and experiments are done to verify the continuous operating capability. The main factors which affect the performance of the proposed isolated gate driver are summarized. This technology provides a novel solution for SiC MOSFET gate driver in HT environment.

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Section: Amplification Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and experiments of isolated gate driver using discrete devices for silicon carbide MOSFET

Jiang

Wang

et al. 2022

IET Power Electronics

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“…Such innovative communication channels allow this to reduce converter volume. Condition monitoring relies on accurately sensing power modules' precursors to aging, like gate leakage current [32] or temperature [33]. With accurate transistor modeling, component aging can be detected before its failure.…”

Section: The Half-bridge Modular Multilevel Convertermentioning

confidence: 99%

Cascaded Smart Gate Drivers for Modular Multilevel Converters Control: A Decentralized Voltage Balancing Algorithm

et al. 2021

Self Cite

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Recent Modular Multilevel Converter (MMC) topology allows for drastic improvements in power electronic conversion such as higher energy quality, lower power semiconductors electrical stress, decreased Electro-Magnetic Interferences (EMI), and reduced switching losses. MMC is widely used in High Voltage Direct-Current (HVDC) transmissions as it offers, theoretically, no voltage limit. However, its control electronic structure is not modular itself. Especially, the insulation voltage between the submodule gate drivers’ primaries and secondaries depends on the number of submodules. The converter voltage levels cannot be increased without designing all gate driver isolations again. To solve that issue, the novel concept of distributed galvanic insulation is introduced for multilevel converters. The submodule’s gate drivers are daisy-chained, which naturally reduces the insulation voltage to the submodule capacitor voltage, regardless of the number of submodules. The MMC becomes truly modular as the number of submodules can be increased without impacting on the previous control electronic circuit. Such an innovative control structure weakens the link between the main control unit and the gate drivers. This inherent structural problem can be solved through the use of Smart-Gate Drivers (SGD), as they are often equipped with fast and bidirectional communication channels, while highly increasing the converter reliability. The innovation proposed in that work is the involvement of smart gate drivers in the distributed galvanic insulation-based MMC control and monitoring. First, the numerous benefits of smart gate drivers are discussed. Then, an innovative Voltage Balancing Algorithm directly integrated on the chained gate drivers is proposed and detailed. It features a tunable parameter, offering a trade-off between accurate voltage balancing and execution time. The proposed embedded algorithm features a low execution time due to simultaneous voltage comparisons. Such an algorithm is executed by the gate drivers themselves, relieving the main control unit in an original decentralized control scheme. A simulation model of a multi-megawatts three-phase grid-tied MMC inverter is realized, allowing validation of the proposed algorithm. Matlab/Simulink logic blocs allow us to simulate a typical CPLD/FPGA component, often embedded on smart gate drivers. The converter with the proposed embedded algorithm is simulated in steady-state and during load impact. The controlled delay and slew rate inferred by the algorithm do not disturb the converter behavior, allowing its conceptual validation.

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“…As a result, measurement for direct SoH estimation has gained high relevance. On-state voltage drop ( ) [5], threshold voltage ( ), thermal resistance ( ) [6], and gate leakage current ( ) [7] are amongst the main variables investigated in the literature.…”

Section: Introductionmentioning

confidence: 99%

Condition monitoring of power module using S-parameters, TDR, and TDT

Pascal

Daschner

Liserre

et al. 2022

Microelectronics Reliability

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Monitoring of Gate Leakage Current on SiC Power MOSFETs: An Estimation Method for Smart Gate Drivers

Cited by 18 publications

References 22 publications

Design and experiments of isolated gate driver using discrete devices for silicon carbide MOSFET

Design and experiments of isolated gate driver using discrete devices for silicon carbide MOSFET

Cascaded Smart Gate Drivers for Modular Multilevel Converters Control: A Decentralized Voltage Balancing Algorithm

Condition monitoring of power module using S-parameters, TDR, and TDT

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