Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node

A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

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A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

Karimi

Ali

Hassan

et al. 2022

IEEE Access

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Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node

Cited by 1 publication

References 18 publications

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

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