Monolithic III-V/Si integration

Fitzgerald, Eugene A.; Bulsara, Mayank T.; Bai, Yuhao; Cheng, C.H.; Liu, W.K.; Lubyshev, D.; Fastenau, J. M.; Wu, Ying; Urtega, M.; Ha, Wonill; Bergman, J.; Brar, B.; Drazek, Charlotte; Daval, N.; Letertre, F.; Hoke, W. E.; LaRoche, J. R.; Herrick, K.J.; Kazior, T.E.

doi:10.1109/icsict.2008.4734819

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…Based on the epitaxial lift-off and transfer technology, the researchers realized the monolithic integration of the digital control switch circuit of GaAs PHEMT and Si CMOS as illustrated in Figure 8(b) [58]. It has been reported that InP heterojunction bipolar transistors (HBTs) can be integrated on Si materials platforms within silicon fabrication facilities [59], as presented in Figure 8(c). Based on the ion-cutting technology [60][61][62][63], the researchers realized different kinds of wafer scale heterogeneous integration materials, e.g., GaAs/Si, InP/Si, LiTaO 3 /Si, LiNbO 3 /Si, SiC/Si, and Ga 2 O 3 /SiC, as shown in Figure 8(d).…”

Section: Cross-dimensional Heterogeneous Integrationmentioning

confidence: 99%

Recent progress of integrated circuits and optoelectronic chips

Xiang

Han

Zhang

et al. 2021

Sci. China Inf. Sci.

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Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called "Moore's law" in the past 60 years, and now has entered the post Moore's law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.

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Section: Cross-dimensional Heterogeneous Integrationmentioning

confidence: 99%

Recent progress of integrated circuits and optoelectronic chips

Xiang

Han

Zhang

et al. 2021

Sci. China Inf. Sci.

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“…On the other hand, III-V materials and their compounds have led to the development of recent optoelectronics and optical communications owing to their outstanding light-emitting properties [4][5][6]. Therefore, one of the approaches that receives increased attention lately is that to integrate III-V materials or their compounds monolithically on Si [7][8][9][10][11]. This approach is anticipated to have the advantages of both the technologies and hence achieving improved device performance along with energy efficiency, package density and product cost [12,13].…”

Section: Introductionmentioning

confidence: 99%

Template-assisted growth of Ga-based nanoparticle clusters on Si: effect of post-annealing process on the Ga ion beam exposed 2D arrays fabricated by focused ion beam nanolithography

Radhakrishnan,

Rangarajan,

Pandian

et al. 2024

Nanotechnology

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We demonstrate template-assisted growth of gallium-based nanoparticle clusters on silicon substrate using a focused ion beam (FIB) nanolithography technique. The nanolithography counterpart of the technique steers a focussed 30 kV accelerated gallium ion beam on the surface of Si to create template patterns of two-dimensional dot arrays. Growth of the nanoparticles is governed by two vital steps namely implantation of gallium into the substrate via gallium beam exposure and formation of the stable nanoparticles on the surface of the substrate by subsequent annealing at elevated temperature in ammonia atmosphere. The growth primarily depends on the dose of implanted gallium which is in the order of 107 atoms per spot and it is also critically influenced by the temperature and duration of the post-annealing treatment. By controlling the growth parameters, it is possible to obtain one particle per spot and particle densities as high as 109 particles per square centimetre could be achieved in this case. The demonstrated growth process, utilizing the advantages of FIB nanolithography, is categorized under the guided organization approach as it combines both the classical top-down and bottom-up approaches. Patterned growth of the particles could be utilized as templates or nucleation sites for the growth of an organized array of nanostructures or quantum dot structures.

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High vertical yield InP nanowire growth on Si(111) using a thin buffer layer

et al. 2013

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We demonstrate the growth of InP nanowires on Si(111) using a thin InP buffer layer. The buffer layer is grown using a two-step procedure. The initial layer formation is ensured by using a very low growth temperature. An extremely high V/III ratio is necessary to prevent In droplet formation at this low temperature. The second layer is grown on the initial layer at a higher temperature and we find that post-growth annealing of the buffer layer does not improve its crystal quality significantly. It is found that the layers inherently have the (111)B polarity. Nanowires grown on this buffer layer have the same morphology and optical properties as nanowires grown on InP (111)B substrates. The vertical yield of the nanowires grown on the buffer layer is over 97% and we also find that crystal defects in the buffer layer do not affect the morphology, vertical yield or optical properties of the nanowires significantly.

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Monolithic III-V/Si integration

Cited by 3 publications

References 2 publications

Recent progress of integrated circuits and optoelectronic chips

Recent progress of integrated circuits and optoelectronic chips

Template-assisted growth of Ga-based nanoparticle clusters on Si: effect of post-annealing process on the Ga ion beam exposed 2D arrays fabricated by focused ion beam nanolithography

High vertical yield InP nanowire growth on Si(111) using a thin buffer layer

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