Monolithic time-to-digital converter with 20ps resolution

Tisa, Simone; Lotito, A.; Giudice, Andrea; Zappa, Franco

doi:10.1109/esscirc.2003.1257173

Cited by 27 publications

(12 citation statements)

References 7 publications

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“…The TDCs presented in [14] and [15] are comparable to the TDC designed in this work since they are designed without any off-chip reference signal. Controlled matching is used to reduce sensitivity with regard to temperature in [15].…”

Section: Measurement Resultsmentioning

confidence: 98%

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

Nissinen

Kostamovaara

2010

Analog Integr Circ Sig Process

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The noise and jitter characteristics of an onchip voltage reference-locked ring oscillator used in the time-to-digital converter (TDC) of the integrated receiver of a pulsed time-of-flight laser rangefinder are presented. The frequency of the ring oscillator, 683 MHz, was locked to the on-chip voltage reference by means of a frequencyto-voltage converter, resulting in better than 90 ppm/°C stability. The noise and jitter transfer characteristics of the loop were derived, and simulations were performed to see the effects of different noise types (white and 1/f noise) on the cumulative jitter of the locked ring oscillator. Finally, these results were verified by jitter measurements performed using an integrated time-to-digital converter (TDC) fabricated on the same die (0.18 lm CMOS process). The cumulative jitter of the on-chip reference-locked ring oscillator was less than 30 ps (sigma value) over a time range of 70 ns, which made it possible to use this oscillator as the heart of a TDC when aiming at centimetre-level precision (1 cm = 67 ps) in laser ranging.

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Section: Measurement Resultsmentioning

confidence: 98%

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

Nissinen

Kostamovaara

2010

Analog Integr Circ Sig Process

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“…As described, the pulse shrinking occurs because of the difference between the falling and the rising delays along the delay chain [2][3][4][5][6]. Without any bias adjustment, the pulse-shrinking mechanism with a dimension-controlled NOT gate was proposed to vary the size of the inhomogeneous (or pulse-shrinking) NOT gate to control the pulse-shrinking amount, as shown in Fig.…”

Section: Conventional Pulse-shrinking Mechanismmentioning

confidence: 99%

“…high resolution). Several previous works applied it to reach sub-gate resolutions [4][5][6]. In this paper, an improved version with adding a simple gate is proposed to achieve better performance in resolution for time measurement.…”

Section: Introductionmentioning

confidence: 99%

“…In additional to an absolute gate delay with an advanced CMOS technology, the approaches such as parallel scaled delay elements, Vernier delay lines, and time amplification can achieve a sub-gate delay resolution at the expense of circuit complexity and area. With low cost and simple circuit operation, the pulse-shrinking method has the possibility of reaching sub-gate resolution but without requiring circuit complexity [2][3][4][5][6]. When a pulse with a finite time width undergoes a pulse-shrinking unit to cause difference between the rising and the falling propagation times, the pulse width is shrinked by a small amount (i.e., time resolution).…”

Section: Introductionmentioning

confidence: 99%

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A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Chen¹,

Chen²,

You³

et al. 2017

dtetr

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Abstract.A new CMOS time measurement mechanism based on pulse shrinking applicable to time-to-digital converters (TDCs) is presented to improve resolution. In previous mechanism, the resolution was determined by controlling size ratio between an inhomogeneous and homogeneous logic gates to achieve sub-gate resolution. By only adding an inhomogeneous gate with identical size on the previous mechanism, the proposed mechanism possesses not only a resolution improvement but also a better resolution fluctuation for process and temperature variations. The proposed work was implemented in a 0.35-µm CMOS process for performance evaluation. The results demonstrated that the proposed mechanism achieves a significant resolution improvement with better resolution insensitivity to the process and temperature variations.

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“…7,8,9,10,11 On the other hand, digital interpolation uses a gate delay to estimate the fractional clock cycles. 12,13,14,15,16,17,18,19,20 A simple TDC consists of a high frequency clock and a counter incremented at each clock edge. In such a case, the resolution is limited by the use of the reference clock frequency.…”

Section: Introductionmentioning

confidence: 99%

Time-to-digital converter based on analog time expansion for 3D time-of-flight cameras

Tanveer

Nissinen

et al. 2014

SPIE Proceedings

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This paper presents an architecture and achievable performance for a time-to-digital converter, for 3D time-offlight cameras. This design is partitioned in two levels. In the first level, an analog time expansion, where the time interval to be measured is stretched by a factor k, is achieved by charging a capacitor with current I, followed by discharging the capacitor with a current I k . In the second level, the final time to digital conversion is performed by a global gated ring oscillator based time-to-digital converter. The performance can be increased by exploiting its properties of intrinsic scrambling of quantization noise and mismatch error, and first order noise shaping. The stretched time interval is measured by counting full clock cycles and storing the states of nine phases of the gated ring oscillator. The frequency of the gated ring oscillator is approximately 131 MHz, and an appropriate stretch factor k, can give a resolution of ≈ 57 ps. The combined low nonlinearity of the time stretcher and the gated ring oscillator-based time-to-digital converter can achieve a distance resolution of a few centimeters with low power consumption and small area occupation. The carefully optimized circuit configuration achieved by using an edge aligner, the time amplification property and the gated ring oscillator-based time-to-digital converter may lead to a compact, low power single photon configuration for 3D time-of-flight cameras, aimed for a measurement range of 10 meters.

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Monolithic time-to-digital converter with 20ps resolution

Cited by 27 publications

References 7 publications

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Time-to-digital converter based on analog time expansion for 3D time-of-flight cameras

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