Moore’s Law for Photonics and Electronics

Radamson, Henry H.; Thylén, Lars

doi:10.1016/b978-0-12-419975-0.00004-0

Cited by 4 publications

(4 citation statements)

References 39 publications

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“…The lattice distortion in Ge due to Sn atoms has to be carefully determined in order to derive Sn composition. The following approach shows how this task was performed by using misfit parameters in the GeSn layers [ 50 , 51 , 52 ]. The misfit parameters were calculated through reading data from the HRRLM of 2 θ for substrate and the epilayer:

…”

Section: Resultsmentioning

confidence: 99%

“…The Poisson ratio is obtained from the corresponding Cijs according to Equation (4), then the lattice constant for GeSn can be determined. The Sn content extracted with high precision can be derived from the lattice constant for a composition, according to the following equation [ 50 , 51 ]:

where θ GeSn is a constant which relates to GeSn alloying and is 0.166 Å for x ≤ 0.20 [ 47 , 48 ]. The calculated Sn contents for GeSn layers from HRRLMs are illustrated in Table 3 .…”

Section: Resultsmentioning

confidence: 99%

“…In comparison to GeSn/Ge, a better candidate for optoelectronic applications is GeSn-on-insulator (GeSnOI). This is a result of the excellent mobility of GeSnOI, in addition to its higher light emission efficiency, higher net gain, great optical confinement, low leakage current, resonator effect, higher operation temperature, lower coupling loss with waveguide, and its greater ease for photonic integration [ 4 , 50 , 51 ].…”

Section: Introductionmentioning

confidence: 99%

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Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications

et al. 2022

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GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285–320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature.

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…”

Section: Resultsmentioning

confidence: 99%

where θ GeSn is a constant which relates to GeSn alloying and is 0.166 Å for x ≤ 0.20 [ 47 , 48 ]. The calculated Sn contents for GeSn layers from HRRLMs are illustrated in Table 3 .…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications

et al. 2022

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“…As Figure 13 shows, in earlier years, the k1 factor is above 0.5 when the imaging has high contrast, and there is no need to implement various PETs. When the k1 factor is below 0.5, it moves to the lowcontrast era, where various PETs are required, such as optical proximity correction (OPC), and source mask optimization (SMO) [146][147][148]. In both high-contrast and low-contrast eras, the patterning has been achieved through single exposure and single etch approach.…”

Section: Advanced Lithography Techniquementioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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