Morphological Transition of Vicinal 4H-SiC Surface Observed during Repeated Annealing

Abstract

Step-bunching has attracted sustained attention due to its remarkable influence on the properties of SiC, which is a versatile functional material in the power and optoelectronic fields. Here, step-bunching morphology on the vicinal 4H-SiC surface is discovered to transform among the morphologies with different step sizes and distribution patterns in repeated annealing experiments. Meanwhile, a multiple-hill-valley model, based on the experimental observations, is adopted to analyze the surface energetics, from which the obtained morphologies are verified to be metastable states that can be steadily maintained and thermally accessible from one another. Moreover, for the purpose of elucidating the surface morphology evolution at an atomic scale, molecular dynamics simulations were performed. The results show that at high temperatures, the fluctuation of the number of steps on the surface is extremely active, while the final morphology depends on the cooling rate. Furthermore, the change in step-bunching structure originates from larger steps splitting and smaller ones merging, along with massive atomic migrations. Finally, during the high-temperature process, the atomic trajectories are basically localized along the peripheries of the (0001) facets. These results provide insights into the mechanisms of step-bunching formation and transformation, which are of referential significance to the preparation and application of SiC for the next generation of nanoelectronic technology.

Width-dependent band gap of arm-chair graphene nanoribbons formed on vicinal SiC substrates by MBE

“…The substrate surface was first etched by H 2 gas for producing a regular facet-andterrace structure with the terrace width of 6 nm (4 H) [14] and 10 nm (6 H) [15]. During the hydrogen etching, the substrate temperature was optimized for making the regular facetand-terrace nanostructures between 1360 • C and 1430 • C. We also prepared a facet-and-terrace nanostructure with wide terraces using 6H-SiC by increasing time for the etching process [16] for comparison. After forming the nanostructure, the substrates were heated at 1050 • C by direct current in the substrate under Si flux for cleaning.…”