Morphology control of tunneling dielectric towards high-performance organic field-effect transistor nonvolatile memory

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

“…[4][5][6] Furthermore, the spatial discreteness of charge trapping sites is beneficial for scaling down of tunneling dielectric and improvement of retention capability. 7,8 In a nano-floating-gate OFET memory, electron and hole trapping into the nano-floating-gate is the mechanism to open a memory window. The quantity of charge trapping is often indirectly derived from the threshold voltage (V T ) shift (DV T ) in device transfer characteristics, with positive and negative DV T corresponding to electron and hole trapping, respectively.…”

“…After routine cleaning of the substrate, Au nanoparticles (Au-NPs) as the nano-floatinggate were prepared by sputtering onto SiO 2 . 7,31 The average NP size is about 10 nm. Then, an approximately 10-nm-thick layer of polystyrene (PS, Sigma-Aldrich, weight-average molecular weight M W ¼ 2000 kg/mol) was deposited on the Au-NPs by spin coating, followed by annealing at 100 C for 15 min to prepare the tunneling dielectric.…”

“…Then, an approximately 10-nm-thick layer of polystyrene (PS, Sigma-Aldrich, weight-average molecular weight M W ¼ 2000 kg/mol) was deposited on the Au-NPs by spin coating, followed by annealing at 100 C for 15 min to prepare the tunneling dielectric. 7,31 Subsequently, 40-nm-thick pentacene was deposited on PS in high vacuum (Kurt J. Lesker, working pressure < 10 À6 mbar) to form a patterned organic active layer. As the final step, Cu top electrodes as the drain and source were deposited on pentacene with a shadow mask.…”

Synergistic effect in organic field-effect transistor nonvolatile memory utilizing bimetal nanoparticles as nano-floating-gate

“…OFET nonvolatile memories are compatible with organic logic circuits, making themselves promising components for future flexible electronic applications. There are three typical approaches to modulate and maintain the channel conductivity in an OFET memory: (1) retainable polarization of a ferroelectric gate dielectric [4,5]; (2) charge trapping into a polymeric gate electret [6][7][8]; and (3) charge trapping into a floating-gate [9][10][11][12][13][14][15][16]. The floating-gate architecture is beneficial for getting good memory retention and endurance, owing to its isolation of carrier transport and charge storage layers with a tunneling dielectric in between.…”

“…The floating-gate architecture is beneficial for getting good memory retention and endurance, owing to its isolation of carrier transport and charge storage layers with a tunneling dielectric in between. Especially, by adopting spatially discrete charge trapping sites, nano-floating-gate applied in an OFET memory can effectively suppress the charge leakage effect and hence improve device retention capability [11,14]. It is also in favor of scaling down the dielectric thickness, which is critical to reduce device programming/erasing bias [17].…”