Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

Abstract

The brain’s connectivity is locally dense and globally sparse, forming a small-world graph—a principle prevalent in the evolution of various species, suggesting a universal solution for efficient information routing. However, current artificial neural network circuit architectures do not fully embrace small-world neural network models. Here, we present the neuromorphic Mosaic: a non-von Neumann systolic architecture employing distributed memristors for in-memory computing and in-memory routing, efficiently implementing small-world graph topologies for Spiking Neural Networks (SNNs). We’ve designed, fabricated, and experimentally demonstrated the Mosaic’s building blocks, using integrated memristors with 130 nm CMOS technology. We show that thanks to enforcing locality in the connectivity, routing efficiency of Mosaic is at least one order of magnitude higher than other SNN hardware platforms. This is while Mosaic achieves a competitive accuracy in a variety of edge benchmarks. Mosaic offers a scalable approach for edge systems based on distributed spike-based computing and in-memory routing.

Efficient sparse spiking auto-encoder for reconstruction, denoising and classification

“…To calculate these values, we considered both the energy required to generate spikes, as well as the energy required to transmit those spikes within the network. For each spike, we estimated that it takes approximately 4.9 pJ to generate [60] and 1.6 pJ to transmit those spikes [61]. Initially, we also considered the energy required for synaptic weight update, however this data was not reported for previous auto-encoders.…”

MoOx Synaptic Memristor with Programmable Multilevel Conductance for Reliable Neuromorphic Hardware

“…Memristive devices have aroused a great deal of research interest due to their use as computing units in brain-inspired artificial neural networks to perform matrix-vector multiplication called “compute-in-memory (CIM)”, which would enable power efficient massively parallel processing and go beyond the von Neumann architecture and break its bottleneck. − As a memristor, its resistance should be switched between at least two basic resistance levels (i.e., strongly resistive state and weakly resistive state). While continuous and memorable regulation of intermediate resistance levels (multilevel switching) is more critical for the storage of multiple bits in mimicking the computational functions of nervous system, mostly it is utilizing different external pulse stimulation schemes (electrical, optical, or electrical–optical stimuli) to operate the memristor and modulate its conductance, and thus the functionalities for adapting different applications. , Regardless, new approaches based on internal material design or device assembly are the most fundamental and desirable, challenging, but achievable, which requires a deep understanding of the relation among the material properties, resistive switching dynamics within the memristor, and the resulting device functionalities. , …”