MP3: Minimizing performance penalty for power-gating of Clos network-on-chip

Chen, Lizhong; Zhao, Lihang; Wang, Rui-Sheng; Pinkston, Timothy M.

doi:10.1109/hpca.2014.6835940

Cited by 44 publications

(17 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Prior works [6,7,9,24,28] as well as results given in this work show that the wakeup latency of on-chip network routers is around 6-12 cycles depending on implementation, which is quite sizable. More importantly, a packet may experience wakeup latency multiple times in the network as more than one router along the packet's path could be powered off.…”

Section: Blocking Problem In Conventional Power-gatingmentioning

confidence: 86%

“…This technique intends to filter out short idle periods that are less than the break-even time 2 to reduce the possibility of encountering a powered-off router. However, the timeout value cannot be too long (around 4 cycles [7,9]) as false filtering essentially wastes the remaining idle cycles that can be exploited by power-gating. Finally, several techniques have been proposed to power-gate individual components within a router [24,25,26].…”

Section: Blocking Problem In Conventional Power-gatingmentioning

confidence: 99%

See 1 more Smart Citation

Power punch: Towards non-blocking power-gating of NoC routers

Chen

Zhu

Pedram

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

Self Cite

View full text Add to dashboard Cite

As chip designs penetrate further into the dark silicon era, innovative techniques are much needed to power off idle or under-utilized system components while having minimal impact on performance. On-chip network routers are potentially good targets for power-gating, but packets in the network can be significantly delayed as their paths may be blocked by powered-off routers. In this paper, we propose Power Punch, a novel performance-aware, power reduction scheme that aims to achieve non-blocking power-gating of on-chip network routers. Two mechanisms are proposed that not only allow power control signals to utilize existing slack at source nodes to wake up powered-off routers along the first few hops before packets are injected, but also allow these signals to utilize hop count slack by staying ahead of packets to "punch through" any blocked routers along the imminent path of packets, preventing packets from having to suffer router wakeup latency or packet detour latency. Full system evaluation on PARSEC benchmarks shows Power Punch saves more than 83% of router static energy while having an execution time penalty of less than 0.4%, effectively achieving near non-blocking power-gating of on-chip network routers.

show abstract

Section: Blocking Problem In Conventional Power-gatingmentioning

confidence: 86%

Section: Blocking Problem In Conventional Power-gatingmentioning

confidence: 99%

Power punch: Towards non-blocking power-gating of NoC routers

Chen

Zhu

Pedram

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

Self Cite

View full text Add to dashboard Cite

show abstract

“…As a low-power instance in the multiple networks, the Catnap [13] guarantees full connectivity by keeping one subnet always active, while keeping other subnets power-gated to reduce unnecessary leakage power. Profiting from the excellent path diversity in the Clos network, the MP3 [14] utilizes minimal router resources and links to ensure all nodes are fully connected, and other remaining full-routers and partial-routers can be power-gated to achieve leakage power-saving. However, the Catnap merely increases the efficiency of power-gating in the architecture of multiple networks, and the MP3 is only applicable to Clos and other indirect networks.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…Originating the idea of guaranteeing full connectivity, these researches [12][13][14] provide a fully connected path to avoid the disconnection problem. The NoRD [12] introduces a bypass ring path to connect all nodes completely; then packets can be transmitted in the bypass ring to avoid long wake-up latency when meeting a sleeping router.…”

Section: Related Work and Motivationmentioning

confidence: 99%

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Wang

Tang

Zhang

2015

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

show abstract

“…MP3 [6] is a methodology to power-gate routers in Clos networks inducing minimal performance overhead. MP3 maintains a set of routers powered on in such a way that all the processing elements in the network remain connected.…”

Section: Power Gating At the Router-level Granularitymentioning

confidence: 99%