MPLEM: An 80-processor FPGA Based Multiprocessor System

Mplemenos, Georgios-Grigorios; Papaefstathiou, Ioannis

doi:10.1109/fccm.2008.15

Cited by 21 publications

(7 citation statements)

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“…This means that, supposing that the size of sub-matrices is [16,16], 256 multiplications and additions are executed at every multiplication period. The general architecture of our design is outlined in Figure 3, and includes three basic pipeline stages: SRAMs with the FPGA is controlled by a control unit which implements the scheme presented in [11]. As the access time to SRAMs is much bigger than that of the built-in reconfigurable device BRAMs, and in order to increase the locality of the data, a control unit reads subblocks of 64x64 entries from the SRAMs.…”

Section: Implimentation Of Matrix Multiplication Unitmentioning

confidence: 99%

A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems

Sotiropoulos

Papaefstathiou

2009

2009 International Conference on Field Programmable Logic and Applications

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In this paper we present a reconfigurable device which significantly improves the execution time of the most computational intensive functions of three of the most widely used face recognition algorithms; those tasks multiply very large dense matrices. The presented architecture utilizes numerous digital signal processing units (DSPs) organized in a parallel manner within a stateof-the-art FPGA device. In order to accelerate those functions we have implemented a "blocked" matrix multiplication algorithm which multiplies certain submatrices of fixed-point 32-bit numbers; the size of the submatrices has been selected so as to fully exploit the resources of the underlying reconfigurable device. Our system is up to 550 times faster than a conventional general purpose processor when implementing the most CPU intensive parts of a number of very widely used Face Identification Schemes, whereas it is more than 40 times faster than the similar schemes implemented in reconfigurable devices. Moreover, our system is general enough so as to be efficiently utilized in any application incorporating fixed-point matrix multiplications.

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Section: Implimentation Of Matrix Multiplication Unitmentioning

confidence: 99%

A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems

Sotiropoulos

Papaefstathiou

2009

2009 International Conference on Field Programmable Logic and Applications

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“…It is depicted the FPGA model, the use of area (S: Slices; FF: Flip-Flops; LUT: Lookup Tables; LE: Logic Elements), the use of on-chip memory, and the maximum speed of the system. [20] 80 MB Net shared mem shared-bus [21] 4 NiosII Net shared mem shared-bus [22] 24MB Net sharedmem NoC [23] 4 MB Net shared mem shared bus [24] n Nios Net shared mem shared bus [16] 16 [29]. This is an extension of the taxonomy proposed and widely accepted by Flynn at 1966 [28] (see Figure 7).…”

Section: Architecture Backgroundmentioning

confidence: 99%

“…Another solution is to use external memory to increase the amount of memory. In this case, the number of external memory blocks is limited by the package and pins of the FPGA [20,22]. If the multiprocessor system does not fit in a single FPGA, it is possible to implement the system using a multi-FPGA approach [33].…”

Section: Design Challengesmentioning

confidence: 99%

Reconfigurable Multiprocessor Systems: A Review

Dorta

Jiménez

Martín

et al. 2010

International Journal of Reconfigurable Computing

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Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.

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“…[17] gives a design of a symmetric multiprocessing on programmable chips using Altera NIOS-II softcore as the basic building block. Similarly, there are many design and implementations of multiprocessor systems using the Xilinx MicroBlaze softcore processor [18][19] [20][21] [22]. The main drawback of all these designs is that they are using proprietory softcores which are not open-source.…”

Section: Related Workmentioning

confidence: 99%

A shared reconfigurable VLIW multiprocessor system

Anjam

Wong

Nadeem

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Abstract-In this paper, we present the design and implementation of an open-source reconfigurable very long instruction word (VLIW) multiprocessor system. This processor is implemented as a softcore on a field-programmable gate arrays (FPGA) and its instruction set architecture (ISA) is based on the Lx/ST200 ISA. This multiprocessor design is based on our earlier ρ-VEX processor design. Since the ρ-VEX processor is a parameterized processor, our multiprocessor design is also parameterized. By utilizing a freely available compiler and simulator in our development framework, we are able to optimize our design and map any application written in C to our multiprocessor system. This VLIW multiprocessor can exploit data level as well as instruction level parallelism inherent in an application and make its execution faster. More importantly, we achieve our results by saving expensive FPGA area through the sharing of resources. The results show that we can achieve two times better performance for our dual-processor system (with shared resources) compared to a uni-processor system or a 2-cluster processor system for applications having data level and instruction level parallelism.

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MPLEM: An 80-processor FPGA Based Multiprocessor System

Cited by 21 publications

References 1 publication

A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems

A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems

Reconfigurable Multiprocessor Systems: A Review

A shared reconfigurable VLIW multiprocessor system

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