mPlogP: A Parallel Computation Model for Heterogeneous Multi-core Computer

Li, Liang; Zhang, Xingjun; Feng, Jianmin; Dong, Xiaoshe

doi:10.1109/ccgrid.2010.60

Cited by 7 publications

(2 citation statements)

References 9 publications

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“…PLogP [41] and mPlogP [42] have been introduced for multicore architectures. The former includes the overhead (sender and receiver), latency, gap message, and number of nodes.…”

Section: Logp Modelmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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“…PLogP [41] and mPlogP [42] have been introduced for multicore architectures. The former includes the overhead (sender and receiver), latency, gap message, and number of nodes.…”

Section: Logp Modelmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

View full text Add to dashboard Cite

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“…Some of them were extended with memory concerns [5,6] and multi-core features [11,16]. Modeldriven algorithm optimization has been tackled in multiple works [9,12] but with almost no cache coherence concerns.…”

Section: Related Workmentioning

confidence: 99%

Cache Line Aware Optimizations for ccNUMA Systems

Ramos

Hoefler

2015

Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing

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Current shared memory systems utilize complex memory hierarchies to maintain scalability when increasing the number of processing units. Although hardware designers aim to hide this complexity from the programmer, ignoring the detailed architectural characteristics can harm performance significantly. We propose to expose the block-based design of caches in parallel computers to middleware designers to allow semi-automatic performance tuning with the systematic translation from algorithms to an analytic performance model. For this, we design a simple interface for cache line aware (CLa) optimization, a translation methodology, and a full performance model for cache line transfers in ccNUMA systems. Algorithms developed using CLa design perform up to 14x better than vendor and open-source libraries, and 2x better than existing ccNUMA optimizations.

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Research on LogGP Based Parallel Computing Model for CPU/GPU Cluster

Song

Ren

et al. 2016

Advances in Intelligent Systems and Computing

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mPlogP: A Parallel Computation Model for Heterogeneous Multi-core Computer

Cited by 7 publications

References 9 publications

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

Cache Line Aware Optimizations for ccNUMA Systems

Research on LogGP Based Parallel Computing Model for CPU/GPU Cluster

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