mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions

Abstract

We present a run-time system for a multi-grained reconfigurable processor in order to provide a dynamic trade-off between performance and available area budgets for both fine-as well as coarse-grained reconfigurable fabrics as part of one reconfigurable processor. Our run-time system is the first implementation of its kind that dynamically selects and steers a performance-maximizing multi-grained instruction set under run-time varying constraints. It achieves a performance improvement of more than 2x compared to state-of-the-art run-time systems for multi-grained architectures. To elaborate the benefits of our approach further, we also compare it with offline-and onlineoptimal instruction-set selection schemes.

Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors

“…13 shows the comparison to policies where resources are given to the tasks with the highest performance improvement factors that is discussed in [18]. Compared to [18], our scheme reduces (on avg.) 6.9x deadline misses and achieve up to 1.4x time performance improvements (avg.…”

“…The approaches in [7][8][9][10]16] have discussed the operating system based task placement and scheduling of complete tasks on the reconfigurable fabric while considering the reconfiguration latency. Authors in [18] discuss run-time techniques for mapping of complete tasks on reconfigurable processors in order to achieve higher performance. In contrast, other approaches discussed in [11,12] target reconfigurable architectures for high performance computing by enabling the sharing of attached FPGAs among parallel applications at compile-time.…”

“…c) Calculate the criticalities based on the remaining time calculated in step b). The criticalities are calculated proportional to 4 details about the estimated execution time of ISE are published in [18] the remaining time of all active tasks that belong to same dependent set of tasks. d) The updated criticality values are then passed to the Constraints-based Resource-Distributor.…”

“…Typically, reconfigurable architectures use Instruction Set Extensions (ISEs) to accelerate the kernels [1,13,14,22]. These ISEs consist of data-paths that may be reconfigured on parts of a fine-grained (FG) or a coarse-grained (CG) reconfigurable fabric [1,18]. It thereby enables different performance vs. area tradeoffs, i.e., different speedups for different utilizations of the reconfigurable fabric.…”

Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures

“…(2) Custom Instruction and Accelerator Selection chooses a particular implementation version at run time from a set of design-time developed implementation versions for each Custom Instruction (called by the concurrently executing tasks). Each custom instruction consist of several datapaths that can be reconfigured on FG reconfigurable elements [10], CG reconfigurable elements, or the combination of both [11].…”