MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture

Das, Tuhin Subhra; Ghosal, Prasun

doi:10.1109/inis.2017.61

Cited by 2 publications

(7 citation statements)

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“…BWA scales linearly, whereas HISAT2 ( Kim et al , 2019 ) shows a decay in execution speed with higher than 4 x 4 network sizes. This is further illustrated by Das and Ghosal (2018) who suggest that the NoC network topology, particularly those relying exclusively on mesh topologies, result in higher latency (slower performance) at higher network dimensions. Joardar et al (2019) among others, identified significant routing constraints with NoCs for genomic data analysis, and add that read alignment algorithms require repeated memory accesses resulting in idle computation units and high latency times ( Joardar et al , 2019 ).…”

Section: Computational Challenges Of Short Read Alignmentmentioning

confidence: 94%

“… NoC mesh and ring topology adapted from Das and Ghosal (2018) . PE, processing element; NI, network interface; R, switching router.…”

Section: Computational Challenges Of Short Read Alignmentmentioning

confidence: 99%

“…Early many-core alignment and NoC implementations such as Subbulakshmi and Balamurugan (2014) and Das and Ghosal (2018) demonstrated NoCs as an enabling mechanism that significantly increases the performance of hardware-based genomic data analysis. However, the correlation between the number of processing cores and transmission delays within the network poses a significant barrier to the implementation of NoC for SRA ( Wang and Wang, 2019 ).…”

Section: Computational Challenges Of Short Read Alignmentmentioning

confidence: 99%

“…The dependence on large external memory significantly limits scalability as the operational cost rises with the number of computational units ( Sarkar et al , 2010 ). However, the use of NoCs has shown potential in mitigating this dedicated RAM dependency through the intelligent management of global and local data memory access ( Das and Ghosal, 2018 ). Initially proposed for short read alignment by Sarkar et al in 2010 , NoC-based hardware demonstrated a 2.5 x 10 4 (reads per second) increase in speed compared to traditional CPU based alignment.…”

Section: Opportunities In Short Read Alignment Accelerationmentioning

confidence: 99%

“… Wang and Wang (2019) further demonstrated the acceleration of popular computational algorithms using a novel NoC-based accelerator. Thus, the NoC paradigm provides a practical interconnection mechanism for enabling high integration of many-core designs with a high degree of modularity and explicit data-parallelism ( Das and Ghosal, 2018 ; Joardar et al , 2019 ; Sarkar et al , 2010 ; Wang and Wang, 2019 ).…”

Section: Opportunities In Short Read Alignment Accelerationmentioning

confidence: 99%

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Hardware acceleration of genomics data analysis: challenges and opportunities

2021

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The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic data analysis. Short read alignment (SRA) is a ubiquitous process within every modern bioinformatics pipeline in the field of genomics and is often regarded as the principal computational bottleneck. Many hardware and software approaches have been provided to solve the challenge of acceleration. However, previous attempts to increase throughput using many-core processing strategies have enjoyed limited success, mainly due to a dependence on global memory for each computational block. The limited scalability and high energy costs of many-core SRA implementations pose a significant constraint in maintaining acceleration. The Networks-On-Chip (NoC) hardware interconnect mechanism has advanced the scalability of many-core computing systems and, more recently, has demonstrated potential in SRA implementations by integrating multiple computational blocks such as pre-alignment filtering and sequence alignment efficiently, while minimising memory latency and global memory access. This paper provides a state of the art review on current hardware acceleration strategies for genomic data analysis, and it establishes the challenges and opportunities of utilising NoCs as a critical building block in next-generation sequencing (NGS) technologies for advancing the speed of analysis.

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