MT-ADRES: multi-threading on coarse-grained reconfigurable architecture

Wu, Kehuai; Kanstein, Andreas; Madsen, Jan; Berekovic, Mladen

doi:10.1080/00207210802213930

Cited by 8 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This paper gives a detailed study of the implementation of the SDR architecture in popular reconfigurable heterogeneous CGRAs, namely MORPHOSYS (Morphoing system) [13], MOLEN (polymorphic processor) [14], and ADRES (architecture for dynamically reconfigurable embedded systems) [15]. Initially, the proposed SDR model is designed and simulated in the Agilent SystemVue software [16].…”

Section: Introductionmentioning

confidence: 99%

An experimental study of coarse-grained reconfigurable system-on-chip-based software-defined radio

Nithiyanantham¹,

Palanisamy²

2016

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture.The proposed CGRA-based SDR implementation is based on dynamic partial reconfiguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater flexibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES reconfigurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 field-programmable gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconfiguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconfiguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures.

show abstract