Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics

ACM Trans. Reconfigurable Technol. Syst.

Ienne

2009

To improve FPGA performance for arithmetic circuits that are dominated by multi-input addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in the past to realize parallel multipliers in VLSI technology; however, the peculiar structure of FPGA logic blocks, coupled with the high cost of the routing network relative to ASIC technology, renders compressors ineffective when mapped onto the general logic of an FPGA. On the other hand, current FPGA logic cells have already been enhanced with carry chains to improve arithmetic functionality, for example, to realize fast ternary carry-propagate addition. The contribution of this article is a new FPGA logic cell that is specialized to help realize efficient compressor trees on FPGAs. The new FPGA logic cell has two variants that can respectively be configured as a 6:2 or a 7:2 compressor using additional carry chains that, coupled with lookup tables, provide the necessary functionality. Experiments show that the use of these modified logic cells significantly reduces the delay of compressor trees synthesized on FPGAs compared to state-of-the-art synthesis techniques, with a moderate increase in area and power consumption.

Section: Fpga Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor

ACM Trans. Reconfigurable Technol. Syst.

Ienne

2009

Section: Fpga Architecturementioning

confidence: 99%

“…Kuon and Rose [19] have recently shown that hard, hand-optimized IP cores-namely DSP and MAC blocks-do not offer tangible performance advantages due to the high cost of routing data to and from these blocks, and mismatches in bitwidth. Previous enhancements to FPGA logic blocks, such as support for binary and ternary addition [1,3,40,41] and carry-chains [8,12,14,18,21], have improved FPGA performance for arithmetic operations. Nonetheless, the performance gap between ASICs and FPGAs remains.…”

Section: Introductionmentioning

confidence: 99%

A novel FPGA logic block for improved arithmetic performance

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

Ienne

2008

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41× compared to adder trees synthesized using ternary adders.

“…The vast majority of carry chains that have been proposed are for different types of adders [8,14,17,18,19]; the carry chains on commercial FPGAs available from Xilinx and Altera also fall into this category. One interesting alternative is a carry chain that allows an Altera-style logic cell to be configured as a 7:2 compressor, which is used for multi-operand addition [20].…”

Section: Related Workmentioning

confidence: 99%

Reducing the pressure on routing resources of FPGAs with generic logic chains

Zgheib

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

et al. 2011

Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors).Inspired by the carry chains, we generalize the idea to connect lookup tables (LUTs) in adjacent logic cells. By exploiting the fracturable structure of LUTs in current FPGA generations, we increase the utilization of the existing LUTs in the logic cell by providing new inputs along the logic chain, but without increasing the I/O bandwidth from the programmable interconnect. This allows us to increase the logic density of the configurable logic cells while reducing demand for routing resources, as long as the mapping tools are able to exploit the logic chains. Our experiments using the combinational MCNC benchmarks and comparing against an Altera Stratix-III FPGA show that the introduction of logic chains reduce the average usage of local routing wires by 37%, with a 12% reduction in total wiring (local and global); this translates to improvements in dynamic power consumption of 18% in the routing network and 10% overall, while utilizing 4% fewer logic cells, on average.