Multi-Chip Module Fabricated by W-CSP Method using Excimer Laser Via-Hole Formation and Cu Plating

Abstract

Recently high-density packaging technologies have been in strong demand in an effort to realize the ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmentally-friendly packaging. The purpose of this study is to propose a fabrication method for a multichip module system using W-CSP technology. In this study, we fabricated a two-chip module with W-CSP using an excimer laser to form via-holes and electro-plating to fill the via-holes. This study has two main new technologies: one is new via-hole formation using an excimer laser that makes small (30 μm diameter) and deep (50 and 100 μm) via-holes, with a micro-lens array used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. The second new technology is new copper electroplating techniques to fill the via-holes which have same diameter (30 μm) and different depths (50 and 100 μm) by controlling additives and agitating conditions. In this study, we fabricated a two-chip module, and both chips were covered by resin simultaneously. The second chip, whose thickness was 50 μm, was mounted on a wafer (first chip) after the first chip had completed the wafer process. The second chip was thinned and mounted by die attachment film (DAF). Next, the mounted chips were spin-coater with polyimide or epoxy resin about 100 μm in thickness. Two types of via-hole with different depths, 50 and 100 μm, were formed by excimer laser to connect the wafer and mounted chip pads. Both types of via-hole had a diameter of about 30 μm. After via-hole formation, seed layers, sputtered Ti and Cu films, are necessary for subsequent copper electro-deposition. Using microscopy measurement, the seed layers were seen to be uniformly formed from the top to the bottom of the via-hole.Using a general mixture of additives, brightener, leveler, and suppressor, the via-holes were completely filled. By controlling the suppressor effect, the 100 μm deep via-holes were perfectly filled with the copper electroplating. Both mechanical agitation and current density are effective to ensure via-hole filling and optimization of these two factors is very important in filling via-holes. Moreover, an additional electroless copper seed layer to increase conductivity near the bottom of the via-hole is also effective to suppress voids there. Finally, the conductivities between the first and second chips were confirmed for the multi-chip module fabricated using W-CSP with excimer laser and copper electro-plating.