Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

Waidyasooriya, Hasitha Muthumala; Chong, Weisheng; Hariyama, Masanori; Kameyama, Michitaka

doi:10.1093/ietele/e91-c.4.517

Cited by 4 publications

(4 citation statements)

References 8 publications

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“…If the processing time of the SDR DBF is longer than the channel coherent time of a mobile wireless system, we can decrease the processing time to meet the flat fading channel operation condition [19] by either reducing the array branches of the SDR DBF or using the parallel processing if the double gate counts are available in FPGA. Previous SDR implementation without MFMO circuit modules such as [8] cannot scalably adapt its hardware configuration to the changing number of antenna branches to save the energy.…”

Section: Methodsmentioning

confidence: 99%

“…In [7], it implements a multi-input-multi-output (MIMO) decoder accelerator on a field programmable gate array (FPGA) and shows a very high performance-cost metric compared with general purpose DSP and application-specific IC implementations. The FPGA is increasingly being considered as a highperformance low-cost reconfigurable device for implementing the SDR and CR applications [8]. The multi-context FPGA is one of the typical dynamically-programmable gate arrays, which can efficiently reuse limited hardware resources in time without hierarchical circuit modules.…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

Mar

Kuo

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYThe hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

Mar

Kuo

et al. 2012

IEICE Trans. Inf. & Syst.

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“…MC-FPGAs have a high degree of redundancy in configuration data between contexts [4], [12]. That is, in MC-FPGAs, less than 3% of configuration data are changed when contexts are switched.…”

Section: Area-efficient Switch Block Architecture and Evaluationmentioning

confidence: 99%

“…Figure 2 shows structure of the MC-switch with four contexts. In an MC-switch, has two major problems [4]. The first problem is that the SRAM-based MC-FPGAs have large area and standby power for the configuration memory.…”

Section: Introductionmentioning

confidence: 99%

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

Ishihara

Idobata

Hariyama

et al. 2010

IEICE Trans. Inf. & Syst.

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SUMMARYDynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiplevalued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multicontext switch block is reduced to 63% in comparison with that of the SRAM-based one. key words: dynamically programmable gate array, multi-context switch, logic-in-memory circuit, multiple-valued threshold logic, nonvolatile storage, non-destructive operation

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Intracranial Hematoma Classification Based on the Pyramid Hierarchical Bilinear Pooling

Zhao

Bao

et al. 2021

Pattern Recognition and Computer Vision

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Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

Cited by 4 publications

References 8 publications

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

Intracranial Hematoma Classification Based on the Pyramid Hierarchical Bilinear Pooling

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