Multi-Core DSP Based Parallel Architecture for FMCW SAR Real-Time Imaging

Gu, Chengfei; Chang, Wenge; Li, X. Y.; Liu, Z. H.

doi:10.13164/re.2015.1084

Cited by 13 publications

(8 citation statements)

References 8 publications

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“…The time and power consumption are less than that of the related design described in [ 22 ] because the proposed system can achieve round-robin assignment in full parallel for both range direction operations. Compared with references [ 2 , 24 , 31 , 19 , 32 ], taking into account the data granularity processed, the proposed system shows advantages in both processing time and power consumption. Although [ 21 ] takes only 2.8 s to process SAR raw data with 32,768 × 32,768 data granularity, the large power consumption of the GPU is unacceptable with respect to the harsh spaceborne on-board real-time processing requirements.…”

Section: Realization Of the Multi-node Prototype Platformmentioning

confidence: 99%

“…For example, four times all-pixel FFTs are the most computation-hungry operations of CS implementation, and the efficiency burden mainly occurs in the data access after corner turning (matrix transposition) [ 22 ]. In a previous study [ 23 ], the window access mode was used to accelerate the matrix transposition, while in another study [ 24 ], ping pong buffers were used for Dual data rate (DDR) SDRAM to solve this problem. However, these approaches have various limitations of universality, e.g., two-dimensional rate mismatch and the method of complicated phase function generation, which can reduce the hardware resource utilization and meets the level of real-time imaging.…”

Section: Introductionmentioning

confidence: 99%

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Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

Shi

Chen

et al. 2018

Sensors

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With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. A key goal of the on-board SAR imaging system design is to achieve high real-time processing performance under severe size, weight, and power consumption constraints. This paper presents a multi-node prototype system for real-time SAR imaging processing. We decompose the commonly used chirp scaling (CS) SAR imaging algorithm into two parts according to the computing features. The linearization and logic-memory optimum allocation methods are adopted to realize the nonlinear part in a reconfigurable structure, and the two-part bandwidth balance method is used to realize the linear part. Thus, float-point SAR imaging processing can be integrated into a single Field Programmable Gate Array (FPGA) chip instead of relying on distributed technologies. A single-processing node requires 10.6 s and consumes 17 W to focus on 25-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. The design methodology of the multi-FPGA parallel accelerating system under the real-time principle is introduced. As a proof of concept, a prototype with four processing nodes and one master node is implemented using a Xilinx xc6vlx315t FPGA. The weight and volume of one single machine are 10 kg and 32 cm × 24 cm × 20 cm, respectively, and the power consumption is under 100 W. The real-time performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging.

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Section: Realization Of the Multi-node Prototype Platformmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

Shi

Chen

et al. 2018

Sensors

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“…In addition, the time and power consumptions are less than those of the related design described in [28] and [29] because the proposed the ASIC has higher integration. Compared with references [2], [33], [34] , [26] and [35] , considering the data granularity processed, the proposed system shows advantages in both processing time and power consumption. Although [12] takes only 2.8 s to process SAR raw data with 32,768×32,768 granularity, the large power consumption of the GPU is unacceptable with respect to the strict spaceborne on-board real-time processing requirements.…”

Section: Experiment Performance and Comparisonmentioning

confidence: 99%

A Multi-mode SAR Imaging Chip based on a Dynamically Reconfigurable SoC Architecture Consisting of Dual-operation Engines and Multilayer Switching Network

Long¹,

Yang²,

B³

et al. 2018

Preprint

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With the development of satellite load technology and very-large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. Limited by severe size, weight, and power consumption constraints, a key challenge of on-board SAR imaging system design is to achieve high real-time processing performance. In addition, with the rise of multi-mode SAR applications, the reconfiguration of the on-board processing system is beginning to receive widespread attention. This paper presents a multi-mode SAR imaging chip with SoC architecture based on the reconfigurable double-operation engines and multilayer switching network. We decompose the commonly used extend chirp scaling (CS) SAR imaging algorithm into 8 types of double-operation engines according to the computing orders, and design a three-level switching network to connect these engines for data transition. The CPU is responsible for engine scheduling based on data flow driven with instructions to implement each part of the CS algorithm. Thus, multi-mode floating-point SAR imaging processing can be integrated into a single Application-Specific Integrated Circuit (ASIC) chip instead of relying on distributed technologies. As a proof of concept, a prototype measurement system with chip-included board is implemented, and the performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. A chip requires 9.2 s, 50.6 s and 7.4 s for a stripmap with 16,384×16,384 granularity, multi-channel stripmap with 65.536×8192 granularity and multi-channel scan mode with 32,768×4096 granularity and 6.9 W for the system hardware to process the SAR raw data.

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“…To reduce the management time of the FAT file system in the embedded storage systems, many revised methods have been proposed by different scholars [11]. For example, a method called new FAT file system (NFAT) is presented by Monsoon Choi.…”

Section: Introductionmentioning

confidence: 99%

A new technology for real-time file system of high-speed storage system in airborne sensors

Tian

Nie

et al. 2021

IEICE Electron. Express

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The airborne sensors with high data rate demand the onboard high-speed storage system due to the limited bandwidth of the downlinks. The NAND Flash and its products are the most common storage medium, and the conventional FAT file system is widely used in the storage systems. However, there has been a problem in recording the live high-speed data stably with this file system. The management time of the FAT file system is relatively long due to the internal overhead which includes the retrieving and updating of the FAT and FDT. The aim of this study is to investigate the technology for the real-time file system. A technology called FPFPA (FAT post-and FDT post-allocation) method is presented to solve this problem. To evaluate the performance of the proposed method, the management time of the file system using our proposed method is tested on the high-speed storage system of an airborne radar. The result indicates that the proposed method achieves our goal successfully in that the management time of the file system is significantly reduced and sufficiently small.

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Multi-Core DSP Based Parallel Architecture for FMCW SAR Real-Time Imaging

Cited by 13 publications

References 8 publications

Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

A Multi-mode SAR Imaging Chip based on a Dynamically Reconfigurable SoC Architecture Consisting of Dual-operation Engines and Multilayer Switching Network

A new technology for real-time file system of high-speed storage system in airborne sensors

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