2016
DOI: 10.1007/978-3-319-48965-0_42
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Multi-core FPGA Implementation of ECC with Homogeneous Co-Z Coordinate Representation

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Cited by 2 publications
(1 citation statement)
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“…Bos [3] introduced a low-latency 7-way GPU implementation of an (X, Z)-only Co-Z ladder for the NIST curve P-224. Peng et al [22] presented an optimized multi-core FPGA implementation of the X-only Co-Z ladder from [13] for a set of Weierstrass curves, whereby they combined a number of Montgomery modular multipliers to work in parallel. They concluded that a 3-core implementation achieves the best throughput-resource ratio.…”
Section: Overview Of Related Work and Motivation For Our Workmentioning
confidence: 99%
“…Bos [3] introduced a low-latency 7-way GPU implementation of an (X, Z)-only Co-Z ladder for the NIST curve P-224. Peng et al [22] presented an optimized multi-core FPGA implementation of the X-only Co-Z ladder from [13] for a set of Weierstrass curves, whereby they combined a number of Montgomery modular multipliers to work in parallel. They concluded that a 3-core implementation achieves the best throughput-resource ratio.…”
Section: Overview Of Related Work and Motivation For Our Workmentioning
confidence: 99%