Multi-core parallel simulation of System-level Description Languages

Domer,; Chen, Guihai; Han, Sang-Min; Gerstlauer,

doi:10.1109/aspdac.2011.5722205

Cited by 15 publications

(7 citation statements)

References 11 publications

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“…However, this model features four parallel slice decoders which decode separate slices in a H.264 frame simultaneously. Specifically, the H.264 stimulus reads new frames from the 2 Due to its similarity, our results are equally applicable to SystemC [4]. input stream and dispatches its slices to the four slice decoders.…”

Section: An Abstract Model Of a Dvd Playermentioning

confidence: 92%

Out-of-order parallel simulation for ESL design

Chen¹,

Han²,

Domer³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits of parallel simulation. This paper presents a new out-of-order simulator for multi-core parallel DE simulation of hardware/software designs at any abstraction level. By localizing the simulation time and carefully handling events at different times, a system model can be simulated following a partial order of time. Subject to automatic static data analysis at compile time and table-based decisions at run time, threads can be issued early which reduces the idle time of available cores. Our experiments show high performance gains in simulation speed with only a small increase of compile time.

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Section: An Abstract Model Of a Dvd Playermentioning

confidence: 92%

Out-of-order parallel simulation for ESL design

Chen¹,

Han²,

Domer³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…For example, we manually wrapped in sc_call some transactions, but the Bus component could do it automatically for user-defined address ranges. This approach can be compared with the SpecC approach, where the language reference allows parallelism within a component, but the communication channels act as monitors [17].…”

Section: Discussionmentioning

confidence: 99%

“…Before the call to extra_time, the during task spans only over [5,10], hence X ∈ [5, 10] is ensured. After calling extra_time, the task spans over [5,17], hence Y ∈ [X, 17]. In general, the semantics of during tasks with extra_time is that a piece of code within the task can be executed at a simulated time t ∈ [s, s + d + e] where s is the starting time of the task, d is the initial duration, and e is the sum of the extra-time accumulated up to this point.…”

Section: ) Full Synchronization With Systemc: Sc_call()mentioning

confidence: 99%

Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach

Moy

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycleaccurate simulation, and would be inefficient on loosely timed systems since they cannot run in parallel processes that do not execute simultaneously.We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. Our tool exploits this notion of duration to run the simulation in parallel. It runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. This allows the user to focus on the performancecritical parts of the program that need to be parallelized.

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“…In [23] an analysis of the execution semantics of both SystemC and SpecC is presented. The authors have implemented an extension to the SpecC simulation kernel to support multi-core simulation.…”

Section: Parallelization Inside Cyclesmentioning

confidence: 99%

“…Following [23], in [29] the authors present a simulator which performs static analysis to prevent data, timing or event conflicts. The technique is similar to branch prediction in hardware.…”

Section: Dependency Analysismentioning

confidence: 99%

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

2016

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Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level.

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Multi-core parallel simulation of System-level Description Languages

Cited by 15 publications

References 11 publications

Out-of-order parallel simulation for ESL design

Out-of-order parallel simulation for ESL design

Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

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