Multi-Disciplinary Digital Signal Processing

Gopi, E. S.

doi:10.1007/978-3-319-57430-1

Cited by 5 publications

(6 citation statements)

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“…The methodology of [32] specifies several steps, which are adapted here for the decimator algorithm as follows: i. The difference equations of the decimator algorithm expressed as an RIA are shown in (1) and (2). ii.…”

Section: Systematic Methodology For Systolic Array Design Applied To mentioning

confidence: 99%

“…We use the powerful systematic technique of [32] to perform systolic array design space exploration of the decimator structure based on the iterations defined by (1) and (2). Fig.…”

Section: Decimator Dgmentioning

confidence: 99%

“…The decimator output y(i) is shown at the top of 0. y(i) is shown by the thick vertical lines since each output sample depends on the i index only. Note that the sample y(i) corresponds to the intermediate sample u(iM), according to (2).…”

Section: Decimator Dgmentioning

confidence: 99%

“…Multirate digital signal processing (DSP) is used in systems, where signals are processed at different data rates [1, 2]. Decimators are used in multirate systems to generate signals with lower data rates.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Fieldprogrammable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

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Section: Systematic Methodology For Systolic Array Design Applied To mentioning

confidence: 99%

“…We use the powerful systematic technique of [32] to perform systolic array design space exploration of the decimator structure based on the iterations defined by (1) and (2). Fig.…”

Section: Decimator Dgmentioning

confidence: 99%

Section: Decimator Dgmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

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Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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“…The powerful systematic technique of reference [17] is used to perform systolic array design space exploration of the interpolator structure based on the iterations defined by (1) and (2). Fig.…”

Section: Interpolator Dependence Graph (Dg)mentioning

confidence: 99%

Systolic array design space exploration of interpolators for multi‐rate systems

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the anti-imaging filter. Different data scheduling and projection operations were developed. Nine systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation. Field-programmable gate array implementations for the conventional and proposed designs confirm that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than the conventional design.

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