Multi DOE Study on 28nm (RF) WLP Package to Investigate BLR Performance of Large WLP Die with 0.35mm Ball Pitch Array

Alvarado, Rey; Keser, Beth; Cui, Tong; Syed, Ahmer; Xu, Susu; Roggeman, Brian

doi:10.1109/ectc.2017.304

Cited by 4 publications

(1 citation statement)

References 15 publications

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“…Table 6 shows the reliability test conditions that the package was qualified for. In FIWLP the use of very stiff alloy solder ball does not lead to solder ball failure but rather transfers the solder ball stress to package RDL, inducing RDL cracking failure [10].…”

Section: Package Reliability Resultsmentioning

confidence: 99%

Development of Wafer Level Package Platform for High Reliability Crossover MCUs

Sharma,

Su,

Thukral

et al. 2024

IMAPSource Proceedings

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Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, solder alloys, solder ball pitch and diameter. Developed packages passed and outperformed the following product reliability qualification conditions: high temperature storage life (150°C, 2000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 528 hours), application level temperature cycling ((-40 °C to 125 °C, 600 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

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Section: Package Reliability Resultsmentioning

confidence: 99%