Multi Fluxon Storage and its Implications for Microprocessor Design

Abstract

One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.

Speeding up qubit control with bipolar single-flux-quantum pulse sequences

“…The considered situation of the bipolar drive signal can be simply implemented by differential connection of two DC-to-SFQ converters driven with a shift of half a clock cycle, see figure 1. Assuming the utilization of a more complex SFQ co-processor, [33] where a tritstream can be hold as two synchronized bit sequences in a standard register file, or as a trit sequence in multibit storage cells [50,51], we further consider this particular case of tritstreams application to a qubit.…”

Microprocessor Design Using COPRAS Method

“…HC-DRO to save content A log file that uses cells We design the structure. HC-DRO is a traditional tube How to design a microprocessor that can be integrated These two are to show The purpose of the demonstrations [12].Compared to other jobs Less than microprocessor design Clock cycles are required. Additionally, the Memory requirements of the microprocessor are relatively small, It only supports AES.…”