Multi-gigabit serial link emissions and mobile terminal antenna interference

Voutilainen, M.; Rouvala, Markku; Kotiranta, P.; Rauner, T. Von

doi:10.1109/spi.2009.5089837

Cited by 18 publications

(12 citation statements)

References 8 publications

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“…In telecommunication area, these technological issues can be sources of distortions, asynchronous effects of the transmitted analog signals and erroneous symbols of numerical data. In order to deal with this difficulty, intensive researches for the enhancement of on-chip interconnects have been conducted [36][37][38][39][40][41]. To estimate the interconnect delay, the most popular method is based on the use of RC-models as introduced by Elmore in 1948 [42][43][44][45][46][47][48][49][50][51][52][53][54].…”

Section: Introductionmentioning

confidence: 99%

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

Eudes

Ravelo

Al-Hayek³

2013

AEM

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This paper is a special issue from the work presented in the Advanced Electromagnetics Symposium 2012 (AES'12) which presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/sinput data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

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Section: Introductionmentioning

confidence: 99%

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

Eudes

Ravelo

Al-Hayek³

2013

AEM

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“…In order to deal with the bottleneck caused by the interconnect imperfection, intensive researches for the enhancements of on-chip interconnect have been conducted [29][30][31][32][33][34][35][36].…”

Section: Introductionmentioning

confidence: 99%

“…In other hand, based on the investigation of row and input flit width in compiled message, a modeling method of hardware performance analysis with Hamming product codes is presented in [32] for the improvement of on-chip interconnect energy. Moreover, new characterization method of serial link bus delay in mobile terminal antennas operating at multi-gigabits speed is described in [33]. Furthermore, a correction method of interconnect degradation by using active circuits with negative group delay is introduced in [34][35][36].…”

Section: Introductionmentioning

confidence: 99%

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

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Abstract-An accurate and behavioral modeling method of symmetrical T-tree interconnect network is successfully investigated in this paper. The T-tree network topology understudy is consisted of elementary lumped L-cells formed by series impedance and parallel admittance. It is demonstrated how the input-output signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of L-cells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the T-tree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multi-level behavioral T-tree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of T-tree topology comprised of different and identical RLC-cells is conducted. To demonstrate the relevance of the model established, lumped RLC T-tree networks with different levels for the microelectronic interconnect application are designed and simulated. The work flow illustrating the guideline for the application of the routine algorithm summarizing the modeling method is proposed. Then, 3D-microstrip T-tree interconnects with width 0.1 µm and length 3 mm printed on FR4-substrate were considered. As results, a very good agreement between the results from the reduced behavioral model proposed and SPICE-computations is found both in frequency-and timedomains by considering arbitrary binary sequence "01001100" with 2 Gsym/s rate. The model proposed in this paper presents significant benefits in terms of flexibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this 24Ravelo work, the modeling of clock T-tree interconnects for packaging systems composed of distributed elements using an analogue process is in progress.

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“…For the better understanding in the matter of the basic functioning of this technology, a large scientific background on the physical approach permitting an accurate analysis of the circuit and system equivalent behaviours or electrical modelling, electromagnetic (EM) effects on the wave propagation and also the mathematical approach for the signal theory are necessary [8][9][10][11][12][13]. The synergy of all these multiphysic fields constitutes the particularity of the signal integrity (SI) discipline which is one of major steps for investigating the analogue and digital high-speed systems.…”

Section: Introductionmentioning

confidence: 99%

“…Beyond the unintentional perturbation phenomena as the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) emissions [8][9], this electronic printed circuit board (PCB) and IC design complexity can generate systematically a serious problematic in terms of SI and power integrity (PI) of the interconnection networks [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Raveloa

2012

Eur. Phys. J. Appl. Phys.

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Abstract:A relevant modelling method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based-on the transfer matrix analysis, the second order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI parameters extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC-and RLC-lines excited by square-wave-pulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well-correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL parameters. Compared to other methods, the computation execution time and data-memory consumed by the program implementing the proposed delay modelling-method algorithm are much better.

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Multi-gigabit serial link emissions and mobile terminal antenna interference

Cited by 18 publications

References 8 publications

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

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