2021
DOI: 10.3390/electronics10182222
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Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

Abstract: RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implement… Show more

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Cited by 10 publications
(3 citation statements)
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“…In such a case, switching the cell may demand several programming cycles in order to get those oxygen ions to drift back [46]. Conversely, if during an RST operation too many ions are displaced, the voltage needed to induce an efficient SET operation in the next programming cycle may not be sufficient, leading the device to be stuck at HRS for several cycles [47,48]. To mitigate soft error impact on memristive networks, it is necessary to design specific circuits able to monitor the effectiveness of each RST/SET operation [18,49].…”
Section: Discussionmentioning
confidence: 99%
“…In such a case, switching the cell may demand several programming cycles in order to get those oxygen ions to drift back [46]. Conversely, if during an RST operation too many ions are displaced, the voltage needed to induce an efficient SET operation in the next programming cycle may not be sufficient, leading the device to be stuck at HRS for several cycles [47,48]. To mitigate soft error impact on memristive networks, it is necessary to design specific circuits able to monitor the effectiveness of each RST/SET operation [18,49].…”
Section: Discussionmentioning
confidence: 99%
“…Considering that the limited precision of RRAM devices intended to map synaptic weights is addressed [10], outcomes derived from this study can be applied to any mapping techniques currently used to implement RRAM-based NN accelerators, namely, (a) multilevel [11], [12], (b) binary [13], (c) unary [14], (d) multilevel with redundancy [15] and (e) slicing [4]. Moreover, this study contributes to the understanding of the conductance variation in RRAMs [16] from an electrical standpoint, which is the first step before enabling accurate analogue computing with imprecise memory devices. Also, although functional silicon-based RRAM NN accelerators have been published in the literature [17,18], we cannot but notice that a demonstrator combining high recognition accuracy combined with analog weight storage and low-power operation is still missing.…”
Section: Introductionmentioning
confidence: 88%
“…In recent times, resistive random-access memory (RRAM) devices have attracted significant attention over the conventional complementary metal oxide semiconductor (CMOS)-based non-volatile memory (NVM) devices. Currently, several research groups have been continuously working on modeling, simulation, fabrication, and engineering of RRAM devices to improve their performance and in exploring their suitability for applications in various fields. There are numerous reports on the resistive switching (RS) behavior of the devices based on binary transition metal oxides (TMOs) such as HfO 2 , ZrO 2 , TiO 2 (stoichiometric films), Cu x O, , TaO x , WO x , and HfO x (sub-stoichiometric films). , HfO 2 and HfO x have received special attention in view of their compatibility with the state-of-the-art Si-based integrated circuit (IC) technology. In previous studies, it was reported that the set and reset voltages are high for the stoichiometric HfO 2 -based RRAM devices . A few reports suggest that the sub-stoichiometric (HfO x ) films may play a critical role in lowering the set and reset voltages , for realizing low-power and energy-efficient devices. …”
Section: Introductionmentioning
confidence: 99%