Multi-level overlay techniques for improving DPL overlay control

Chen, Charlie; Pai, Yuan Chi; Yu, Dennis; Pang, Peter S.; Yu, Chun Chi; Wu, Robert; Huang, Eros; Chen, Marson; Tien, David; Choi, DongSub

doi:10.1117/12.915711

Cited by 5 publications

(2 citation statements)

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“…As a consequence, the prediction of model parameters for exposure by APC becomes precise and finally achieves reduced residual correctable terms in the overlay data. 1 We compared wafer scaling and the total mean plus three sigma before and after implementation of the multiple-pass cascading model ( fig. 12).…”

Section: Hvm Overlay Resultsmentioning

confidence: 99%

An investigation of high-order process correction models and techniques to improve overlay control by using multiple-pass cascading analysis at an advanced technology node

et al. 2013

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Shrinking semiconductor device nodes are driving continuous overlay improvement. This, in turn, is driving broad adoption of high-order control, especially at today's advanced nodes. There are two main categories of high-order control: wafer alignment, and process correction. This paper focuses on the inherent disadvantages of high-order process correction models due to data noise and the deterioration of model term stability. In our study, we observed that linear model terms became unstable after the implementation of high-order process corrections, and observed correlations between model parameters. We investigated correlations for both linear and high-order models, and found that all correlation combinations for the linear model had a Pearson correlation coefficient below 0.25, while 22% of the correlation combinations for third order polynomial parameters had a correlation coefficient greater than 0.5.A high correlation coefficient indicates that similar overlay signatures on the wafer can be modeled by different terms, and that there is instability of model terms in the presence of data noise. Advanced process control (APC) corrections are based on historical lot-to-lot model terms, and are applied to each new lot to be exposed. The instability of model terms adversely affects the precise prediction for a new lot. An alternative solution is to use cascading analysis, which calculates the model parameters sequentially using a series of models. The inherent disadvantage of cascading analysis is loss of model fidelity; however, the robust data filtering scheme used in cascading analysis ensures better overlay stability, as shown in the results of this study.This study shows that cascading analysis consistently yields a lower correlation within and across a batch of lots, but with improved overlay control. Several methods of cascading analysis were investigated in terms of the sequence of linear and high-order modeling. This was done to determine the optimal method for implementing cascading analysis, and to determine the implications of cascading analysis in today's high-volume mass production fabrication facility.

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Section: Hvm Overlay Resultsmentioning

confidence: 99%

An investigation of high-order process correction models and techniques to improve overlay control by using multiple-pass cascading analysis at an advanced technology node

et al. 2013

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“…Even for the same OVL target, different OVL values can be reported by different measurement conditions or different targets. [1][2][3][4][5][6] For example, different color filter selection can report different OVL values, specifically when the OVL target exhibits asymmetry (for either current or previous layer). Therefore, measurement conditions which are defined in the measurement recipe need to be optimized to provide the correct OVL.…”

Section: Accurate Ovl Measurementmentioning

confidence: 99%

Device-correlated metrology for overlay measurements

Chen

Huang

Pai

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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Abstract. One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

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