Multi-level texture caching for 3D graphics hardware

Abstract

Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval of texture during rasterization, and the application is responsible for managing this memory. The push architecture has a bandwidth advantage, but disadvantages of limited texture capacity, escalation of accelerator memory requirements (and therefore cost), and poor memory utilization. The push architecture also requires the programmer to solve the binpacking problem of managing accelerator memory each frame. More recently graphics hardware on PC-class machines has moved to an implementation of what we call the pull architecture.Texture is stored in system memory and downloaded by the accelerator as needed. The pull architecture has advantages of texture capacity, stems the escalation of accelerator memory requirements, and has good memory utilization. It also frees the programmer from accelerator texture memory management. However, the pull architecture suffers escalating requirements for bandwidth from main memory to the accelerator. In this paper we propose multi-level texture caching to provide the accelerator with the bandwidth advantages of the push architecture combined with the capacity advantages of the pull architecture. We have studied the feasibility of 2-level caching and found the following: (1) significant re-use of texture between frames; (2) L2 caching requires significantly less memory than the push architecture; (3) L2 caching requires significantly less bandwidth from host memory than the pull architecture; (4) L2 caching enables implementation of smaller L1 caches that would otherwise bandwidth-limit accelerators on the workloads in this paper. Results suggest that an L2 cache achieves the original advantage of the pull architecturestemming the growth of local texture memory -while at the same time stemming the current explosion in demand for texture bandwidth between host memory and the accelerator.

Cache performance for multimedia applications

“…It was found that although it has been suggested that caches are critically inefficient for video data (several media processor chips dispense with data caches entirely), there was sufficient reuse of values for caching to significantly reduce the raw required memory bandwidth. [17], [10], and [39] study the usefulness of caching the textures used in 3D rendering. A texture cache with a capacity as small as 16 KB has been found to reduce the required memory bandwidth three to fifteen times over a non-cached design and exhibit miss ratios around 1% [17].…”

Inverse texture synthesis

“…Finally, it can be combined with a hardware rendering pipeline, functioning in that context like a mipmap texture cache. We believe that many observations made in previous texture caching papers [7,2,10] could be applied in our algorithm, which has similar (but not identical) characteristics. For example, both texture caching and our algorithm perform better when the access pattern exhibits good coherence.…”

Efficient management of last-level caches in graphics processors for 3D scene rendering workloads

“…The bilinear, trilinear, and anisotropic filters applied to texture stored in the form of a MIP map pyramid [48] offer significant amount of spatial and temporal locality. This observation has inspired a large number of studies on texture cache architectures including single-level texture caches [13], two-level texture caches [7], texture caches in parallel renderers [16,47], prefetching into texture caches with deep FIFO structures [1,17,26,45], victim caching [6], four-dimensional and six-dimensional tiling of texture data [13], and customized DRAM architectures for fast texture access [8,43]. A texture cache architecture with on-the-fly decompression of texture data from a second level compressed texture cache has also been explored [45].…”