Multi-level topology evaluation for ultra-efficient three-phase inverters

Anderson, Jon Azurza; Schrittwieser, Lukas; Leibl, Michael; Kolar, Johann W.

doi:10.1109/intlec.2017.8214178

Cited by 18 publications

(17 citation statements)

References 13 publications

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“…Following the same argumentation, the dimensioning of the capacitance of the FCs, which depends on the maximum conduction time, (3) shown in Fig. 5, remains similar for the FCC and the HANPC converter [9], [12], [23], since the product of N FC,cell and f sw remains similar. Hence, the dimensioning of the flying capacitors follows (4) where I ac,pk is the peak AC current, and ΔU FC,max the maximum allowed peak-to-peak FC voltage ripple.…”

Section: Principle Of Operation Of the Hanpc Convertermentioning

confidence: 99%

“…9. The optimization routine is conducted according to the converter dimensioning guidelines presented in [9], where for the FC stage, four different types of switches are considered, switching in a frequency range between 10 kHz and 40 kHz:…”

Section: Design Optimizationmentioning

confidence: 99%

“…This is advantageous, since the higher the voltage rating of the capacitors, the lower the capacitance density, and hence, more capacitors have to be arranged in parallel and/or series, as can be seen, e.g., for the case of a thirteen-level FCC in [18]. These characteristics of the HANPC converter outperform the FCC in terms of achieving higher power densities for ultra-efficient converters, in particular for three-phase inverters in the 10 kW range targeting 99.5% efficiency, as shown in a comprehensive multi-level topology evaluation done in [9]. Therefore, this paper focuses on the optimization and hardware realization of an all-silicon ultra-efficient passivelycooled 12.5 kW three-phase seven-level HANPC (7L-HANPC) inverter, and finally experimentally verifies a peak efficiency of 99.35% and a power density of 3.4 kW/dm 3 (55.9 W/in 3 ) [20].…”

mentioning

confidence: 97%

“…2(a) for the case of seven levels. Multi-level converters reduce the inductance requirement of the AC-side inductors for a given current ripple amplitude quadratically with respect to the number of levels, due to the multi-level output voltage characteristic and the increase of the effective switching frequency, leading to smaller and more efficient magnetic components [9], [10]. Additionally, multi-level converters take advantage of low-voltage power MOSFETs, featuring a higher hard-switching figure of merit (FOM) compared to high-voltage power semiconductors [11].…”

mentioning

confidence: 99%

“…To achieve a multi-level output voltage characteristic with an FCC, capacitors carrying an integer multiple of the lowest cell voltage are alternatingly connected to the output during operation. However, the capacitance requirement of the flying capacitors (FCs), driven by the need to constrain the switching frequency voltage ripple across them, is directly proportional to the load current (and hence, output power) and inversely proportional to the switching frequency [9]. Accordingly, ultra-high power densities can be achieved at the expense of an efficiency reduction by using high switching frequencies (in the hundreds of Fig.…”

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All-Silicon 99.35% Efficient Three-Phase Seven-Level Hybrid Neutral Point Clamped/Flying Capacitor Inverter

et al. 2019

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With the increasing use of photovoltaic systems, a large demand for efficient, power-dense and lightweight grid-interface inverters is arising. Accordingly, new concepts like multi-level converters, which are able to reduce the converter losses while still keeping a low construction volume, have to be investigated. The hybrid seven-level topology analyzed in this paper comprises an active neutral point clamped stage, followed by a flying capacitor stage. Compared to a pure flying capacitor converter, the combination of these two stages allows to save more than half of the capacitor volume, while still having the same requirement for the output filter stage, and hence, the same output filter volume. Moreover, the topology employs low-voltage devices and ensures low conduction and switching losses, resulting in a higher efficiency. The principle of operation of the system is briefly reviewed, and based on a detailed component modeling, an efficiency vs. power density optimization is carried out, for which switching loss measurements of state-of-the-art 200 V semiconductors are performed. From the optimization, a high-efficiency design is selected and the practical hardware realization is discussed. The simulation and optimization results are then verified by realizing an all-silicon 99.35% efficient three-phase seven-level system, featuring a volumetric power density of 3.4 kW/dm 3 (55.9 W/in 3 ), a gravimetric power density of 3.2 kW/kg, and fulfilling CISPR Class A EMI requirements. Finally, it is shown that an all-silicon realization with next generation silicon switches can achieve 99.5% efficiency with the same hardware, and 99.6% with commercial state-of-the-art GaN switches. Index Terms-Flying capacitor converter, hybrid active neutral point converter, multi-level, PV inverter, ultra-high efficiency. I. IntroductIonA S photovoltaic (PV) energy generation provides a continuously increasing share to the net electricity supply [1], [2], there is a clear demand for power electronics with high efficiency, high power density, low weight and low costs [3]- [6]. For PV systems with high capacity factors, which are in operation for many hours a day, a high energy conversion efficiency is of major importance [7]. With the goal of exploring Manuscript received

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Section: Principle Of Operation Of the Hanpc Convertermentioning

confidence: 99%

Section: Design Optimizationmentioning

confidence: 99%

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confidence: 97%

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All-Silicon 99.35% Efficient Three-Phase Seven-Level Hybrid Neutral Point Clamped/Flying Capacitor Inverter

et al. 2019

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Comprehensive modeling and formulation of split DC link capacitors balancing problem in Three-Phase Three-Level bidirectional AC/DC converters operating with arbitrary power factor

Vule,

Siton,

Kuperman

2023

Alexandria Engineering Journal

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All‐SiC 99.4%‐efficient three‐phase T‐type inverter with DC‐side common‐mode filter

Anderson,

Marciano,

Huber

et al. 2023

Electronics Letters

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This letter presents a hardware demonstrator of an all-SiC three-level T-type (3LTT) inverter with the common-mode (CM) EMI filter stages placed on the DC input instead of the AC output side, targeting, for example, high-efficiency PV applications. The extensive experimental characterization shows that state-of-the-art SiC transistors and a DCside CM filter enable an unprecedented peak/full-load efficiency of 99.4% (calorimetric measurement) at 12.5 kW and a power density of 2.4 kW/dm 3 (39 W/in 3 ). The demonstrator fulfills CISPR 11 Class A EMI regulations as well as upcoming EMI standards for the frequency range of 9-150 kHz. Compared to other high-efficiency converters, which often employ bridge legs with more output voltage levels, the described 3LTT concept thus offers a very favorable trade-off between complexity and performance.

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Multi-level topology evaluation for ultra-efficient three-phase inverters

Cited by 18 publications

References 13 publications

All-Silicon 99.35% Efficient Three-Phase Seven-Level Hybrid Neutral Point Clamped/Flying Capacitor Inverter

All-Silicon 99.35% Efficient Three-Phase Seven-Level Hybrid Neutral Point Clamped/Flying Capacitor Inverter

Comprehensive modeling and formulation of split DC link capacitors balancing problem in Three-Phase Three-Level bidirectional AC/DC converters operating with arbitrary power factor

All‐SiC 99.4%‐efficient three‐phase T‐type inverter with DC‐side common‐mode filter

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