Multi-Module Multi-Port Memory Design for Low Power Embedded Systems

Abstract

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods.

A queue based mutual exclusion algorithm

“…Such weaker memories are increasingly used in smart-phones, multi-mode handsets, multiprocessor systems, network processors, graphics chips, and other high performance electronic devices [6,19,20]. The applicability of our algorithm for weaker memory with safe and write-safe variables increases its practical value for systems with multi-port memories.…”

Nonatomic dual bakery algorithm with bounded tokens

“…Nonatomic algorithms may become practically relevant now, because several recent systems such as smart-phones, multi-mode handsets, network processors, graphics chips, and other high performance electronic devices use multiport memories, and such memories allow nonatomic accesses through multiple ports [14,31,39].…”

Mutual exclusion by four shared bits with not more than quadratic complexity

“…Similarly, algorithms for nonatomic shared variables are becoming practically relevant, because several recent systems such as smart-phones, multi-mode handsets, multiprocessor systems, network processors, graphics chips, and other high performance electronic devices use multiport memories, and such memories allow nonatomic accesses through multiple ports [17,26,28].…”