Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age

Rezaei, Amin; Zhao, Dixian; Daneshtalab, Masoud; Zhou, Hai

doi:10.1109/pdp.2017.12

Cited by 18 publications

(9 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another task mapping i.e. RRM approach for HWNoC is introduced in [10] which avoids congestion by balancing the usage of wireless links over wireless routers.…”

Section: Related Workmentioning

confidence: 99%

“…Consequently, there is a possibility of creating hotspots in these neighboring clusters. Moreover, the RRM algorithm [10] also minimizes the usage of WLs to reduce congestion around WLs. Furthermore, it is worth mentioning that the use of real application task graphs is not considered in [10].…”

Section: Related Workmentioning

confidence: 99%

“…The strategy for placing the optimal number of WRs across the network is discussed in [9]. However, placing limited WRs in HWNoC can create hotspots in the network and make each WR highly vulnerable to congestion [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Cluster Based Adaptive Multi-Voltage Scaling Dynamic Task Mapping for WNoC and HWNoC

Ghosh,

Agarwal,

Sinha

et al. 2024

Preprint

View full text Add to dashboard Cite

Wireless Network-on-Chip (WNoC) and Hybrid Wireless Network-on-Chip (HWNoC) architectures are promising solutions for future high-performance computing systems. However, WNoC consumes significant power, while HWNoC experiences congestion over the wireless link. Several state-of-the-art task mapping algorithms have been proposed to reduce power consumption and congestion over wireless links. However, these existing task mapping algorithms face challenges related to hotspots creation, sub-optimal utilization of wireless links, and also overlook idle core power reduction strategy. Additionally, each of the existing task mapping algorithms is designed for a specific architecture, either WNoC or HWNoC. To address these challenges we propose a novel task mapping algorithm called Cluster-Based Adaptive Multi-Voltage Scaling (CB-AMS). This algorithm dynamically maps tasks to clusters while performing multi-voltage scaling based on workload to significantly reduce power consumption and congestion over wireless links. A new cluster selection strategy is also proposed in CB-AMS to address the hotspot creation issue. CB-AMS is designed to be used in both WNoC and HWNoC architecture. Experimental results show that CB-AMS significantly reduces power consumption by 41% for WNoC and by 15-20% for HWNoC compared to state-of-the-art task mapping algorithms. Experimental results also validate that CB-AMS achieves better congestion control in HWNoC architecture by reducing latency by 3.6-5.5% compared to existing task mapping algorithms. Our experimental analysis has demonstrated that CB-AMS outperforms the current algorithms and delivers significant power reduction and improved congestion control for both WNoC and HWNoC architectures.

show abstract

“…Another task mapping i.e. RRM approach for HWNoC is introduced in [10] which avoids congestion by balancing the usage of wireless links over wireless routers.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Cluster Based Adaptive Multi-Voltage Scaling Dynamic Task Mapping for WNoC and HWNoC

Ghosh,

Agarwal,

Sinha

et al. 2024

Preprint

View full text Add to dashboard Cite

show abstract

“…The task mapping scheme for the HWNoC is investigated [53] where the utilization for wireless connections is balanced by keeping away from congestion over the routers and then spreading the temperature among the entire chip using dark silicon. The outcome of the simulation illustrates a good enhancement in congestion and temperature versus other methods called RRM.…”

Section: Congestion-aware Schemesmentioning

confidence: 99%

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

Màsdàrí

2023

Preprint

View full text Add to dashboard Cite

One of the main stages of Network on Chip (NoC) is task mapping where the application tasks are mapped to the processing resources. Task mapping decisions have a direct impact on the NoC performance and can be classified as static or dynamic mapping methods. In this paper, we carry out a comprehensive systematic study of task mapping schemes in various NoCs. For this purpose, firstly, an overview of the task mapping's main concepts is presented. Then, a taxonomy of the mapping schemes regarding their objectives and applied mapping factors is presented and the studied schemes are categorized into fault-tolerant schemes, congestion-aware schemes, communication-aware approaches, temperature-aware methods, and energy-aware schemes. Afterward, their main contributions, provided services, and drawbacks of the proposed studies in the literature are illustrated. Moreover, a comprehensive discussion of various features of the investigated mapping methods is presented and issues such as the applied algorithms, simulators, datasets, and evaluation metrics are discussed. Finally, the concluding issues and open research areas are highlighted.

show abstract

“…Similarly, Aghaaliakbari et al [33] propose a contiguous mapping algorithm which positions dark nodes in between application tasks to reduce heat. Rezaei et al [34] also proposed a contiguous mapping algorithm contiguous mapping algorithm called Round Rotary mapping which targets a hybrid Wireless NoC virtually divided into regions. The proposed algorithm map applications in a round robin approach to evenly distribute applications all over the chip.…”

Section: Application Mappingmentioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

View full text Add to dashboard Cite

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

show abstract

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age

Cited by 18 publications

References 13 publications

Cluster Based Adaptive Multi-Voltage Scaling Dynamic Task Mapping for WNoC and HWNoC

Cluster Based Adaptive Multi-Voltage Scaling Dynamic Task Mapping for WNoC and HWNoC

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Contact Info

Product

Resources

About