Multi-run Memory Tests for Pattern Sensitive Faults

Mrozek, Ireneusz

doi:10.1007/978-3-319-91204-2

Cited by 10 publications

(12 citation statements)

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“…In a digital system, a comparison of the logical behavior of the tested system with the behavior of the good system is often used when conducting the test. Therefore, there is a need for all physical failures during manufacturing to be modeled as logical faults [5].…”

Section: Memory Functional Fault Modelsmentioning

confidence: 99%

A review paper on memory fault models and test algorithms

Jidin

Hussin

Fook³

et al. 2021

Bulletin EEI

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Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

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Section: Memory Functional Fault Modelsmentioning

confidence: 99%

A review paper on memory fault models and test algorithms

Jidin

Hussin

Fook³

et al. 2021

Bulletin EEI

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show abstract

“…Note that the results obtained for can be easily generalized to other classes of pattern sensitive faults, since is the memory fault model that is most difficult to detect and that covers other types of faults [ 13 , 14 , 25 ]. The number of all possible for

with the N bits is determined according to expression ( 1 ) [ 13 , 26 ].

…”

Section: Transparent Testsmentioning

confidence: 99%

“…The maximum possible number of

detected faults when using a single run march test is determined according to ( 2 ) [ 13 , 26 ].

…”

Section: Transparent Testsmentioning

confidence: 99%

“…With a single application of march tests, including their transparent versions, the fault coverage of , along with any other faults, remains unchanged [ 13 , 25 ]. The only difference is the specific configurations of faults, which are detected (or not detected) by a transparent test with a fixed memory content and a given sequence of addresses [ 9 , 26 ]. Changing the contents of the memory during the operation of the computer system can significantly increase the fault coverage of with repeated use of transparent march tests [ 28 ].…”

Section: Double Address Sequencesmentioning

confidence: 99%

“…To improve the efficiency of multiple uses of march tests, a radical approach involves changing the sequence of addresses used in each of the subsequent iterations of the march test [ 25 ]. The range of uses of different address sequences is quite wide and was investigated in the frameworks of multiple tests [ 26 , 30 , 31 ]. The focus was on the choices of address sequences and their various modifications [ 13 ].…”

Section: Double Address Sequencesmentioning

confidence: 99%

See 2 more Smart Citations

Transparent Memory Tests Based on the Double Address Sequences

Mrozek

Yarmolik

2021

Entropy

Self Cite

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An important achievement in the functional diagnostics of memory devices is the development and application of so-called transparent testing methods. This is especially important for modern computer systems, such as embedded systems, systems and networks on chips, on-board computer applications, network servers, and automated control systems that require periodic testing of their components. This article analyzes the effectiveness of existing transparent tests based on the use of the properties of data stored in the memory, such as changing data and their symmetry. As a new approach for constructing transparent tests, we propose to use modified address sequences with duplicate addresses to reduce the time complexity of tests and increase their diagnostic abilities.

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Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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Multi-run Memory Tests for Pattern Sensitive Faults

Cited by 10 publications

References 0 publications

A review paper on memory fault models and test algorithms

A review paper on memory fault models and test algorithms

Transparent Memory Tests Based on the Double Address Sequences

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

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