Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

Sukharev, Valeriy; Kteyan, Armen; Choy, Jun‐Ho; Hovsepyan, Henrik; Markosian, Ara; Zschech, Ehrenfried; Huebner, Rene

doi:10.1007/s10836-011-5259-y

Cited by 12 publications

(8 citation statements)

References 6 publications

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“…We further note that in the new physics-based EM model, one needs to explicitly consider the residual stresses, σ Res , which can have huge impacts on the nucleation time and thus the failure time of a wire. As a result, it is important to have an accurate estimation of residual stresses and more accurate residual stress can be computed using multi-scale numerical method [13].…”

Section: B Physics-based Em Modelmentioning

confidence: 99%

EM-based on-chip aging sensor for detection and prevention of counterfeit and recycled ICs

Huang

Tan

2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The counterfeiting and recycled integrated circuits (ICs) has become a major security threat for commercial and military systems. In addition to the huge economic impacts, they post significant security and safety threats on those systems. In this paper, we propose a new lightweight on-chip aging sensor, which is based on the electromigration (EM)-induced aging effects for fast detection and prevention of recycled ICs. Our new EM-based aging sensor exploits the natural aging/failure mechanism of interconnect wires to time the aging of the chip. Compared with existing aging sensor, the new aging sensor can provide more accurate prediction of the chip usage time at smaller area footprints due to its simple structure. The new sensor is based on a newly proposed physics-based stress evolution model of EM effects for accurate prediction of the EM failure. As a result, we can design the interconnect wire structures based on copper interconnect technology so that the resulting wires will have detectable EM failure at a specific time with sufficient accuracy. In order to mitigate the problem of the inherent variations in the metal grain sizes and assess its impacts on the nucleation time of metal wires, a number of parallel properly structured wires are used in the sensor. The parameters of the wires are optimized using the new EM model. Our statistical and variational analysis shows that the proposed aging sensor can accurately predict the targeted failure times in the presence of both inherent uncertainties. Our study also shows that more parallel wires will lead to more accurate statistical predictions at costs of more areas.

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Section: B Physics-based Em Modelmentioning

confidence: 99%

EM-based on-chip aging sensor for detection and prevention of counterfeit and recycled ICs

Huang

Tan

2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…In addition to morphology, stress also affects the growth rates of the interfacial Cu Sn t h ¶ ¶ will slow down according to (10), i.e., the growth of the Cu 6 Sn 5 phase will be slower than that in the stress-free condition. Therefore, the difference in the strain energy of the phases cannot explain the enhanced growth of the interfacial Cu 6 Sn 5 phase under tensile stress as illustrated in Fig.…”

Section: A Effects Of Stress On the Morphology And Growth Rate Of Inmentioning

confidence: 99%

“…Efficient chip/package co-analysis of mechanical stress has been enabled by lateral and vertical linear superposition (LVSI) methods developed by Jung et al [8]. However, high-fidelity predictions of stress distribution across chips and packages are still restricted by the lack of a database of multi-scale and timedependent materials properties [1], [10]. In particular, knowledge of microstructuredependent properties still remains scarce.…”

Section: Introductionmentioning

confidence: 99%

Effects of Stress and Electromigration on Microstructural Evolution in Microbumps of Three-Dimensional Integrated Circuits

Xiong

Huang

Conway

2014

IEEE Trans. Device Mater. Relib.

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“…Recently, there were reports on the development of the design verification tool for stress assessment in 3D IC chips, as well as for analysis of the layout-induced transistor-totransistor stress variation generated by various strain engineered sources [8][9]. These sources include the contact etch stop layers (CESL), the variety of stress memorization techniques (SMT), epi-silicon-germanium embedded into the source/drain region, as well as the shallow trench isolation regions (STI).…”

Section: Introductionmentioning

confidence: 99%

“…In this paper we report the novel post-placement simulation algorithm and flow developed for reduction in the off-state leakage current of MOSFET devices with aforementioned layout stress analyzer [8][9]. We demonstrate the simulation results obtained on the standard-cell logic block of the 28 nm test-chip and compare them with measurements.…”

Section: Introductionmentioning

confidence: 99%

Post placement leakage reduction with stress-enhanced filler cells

Choy

Sukharev

Kteyan³

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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A novel methodology for the post placement leakage reduction based on employment of the stress-enhanced filler (SEF) cells was developed. Desired reduction of subthreshold leakage in test chip silicon was achieved by placement of SEF cells close to the most leaking devices. In the standard cell rows the "optimization zones", representing portions of the row located between two consecutive fixed cells (clock cells, etc.), were defined. Mentor Graphics' stress assessment tool was used to find the optimal locations for SEF insertion inside each zone, providing the maximal increase of threshold voltage of the leakiest transistors. Measurements performed on the processed silicon test chip have confirmed the predicted leakage reduction of 10-15 percent while keeping same electrical performance.

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Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

Cited by 12 publications

References 6 publications

EM-based on-chip aging sensor for detection and prevention of counterfeit and recycled ICs

EM-based on-chip aging sensor for detection and prevention of counterfeit and recycled ICs

Effects of Stress and Electromigration on Microstructural Evolution in Microbumps of Three-Dimensional Integrated Circuits

Post placement leakage reduction with stress-enhanced filler cells

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