Multi-silicon ridge nanofabrication by repeated edge lithography

Zhao, Yiping; Berenschot, J.W.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, M.

doi:10.1088/0957-4484/20/31/315305

Cited by 27 publications

(30 citation statements)

References 23 publications

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“…For instance, the creation of a sub-100 nm aperture at the apex of a tip is not at all straightforward in planar lithography due to alignment and step coverage issues. Self-aligned schemes have the ability to overcome this problem [43][44][45][46][47]. The corner lithography method [48][49][50][51][52][53][54], which is applied in this paper, is an example of such a self-aligned technique.…”

Section: Introductionmentioning

confidence: 99%

Wafer-scale fabrication of nanoapertures using corner lithography

Burouni¹,

Berenschot²,

Elwenspoek³

et al. 2013

Nanotechnology

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Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated-based on a theoretical foundation including a statistical analysis-with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

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Section: Introductionmentioning

confidence: 99%

Wafer-scale fabrication of nanoapertures using corner lithography

Burouni¹,

Berenschot²,

Elwenspoek³

et al. 2013

Nanotechnology

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“…Another technique based on the definition of nanoridges by means of successive wet etching and oxidation is reported in Ref. [4].…”

Section: Nanowire Technologiesmentioning

confidence: 99%

“…However, if the accuracy of the alignment is of highest interest, the top-down approaches are more promising candidates, allowing for the arrangement of nanowire layers with a pitch down to a few tens of nanometers. 4 In this work, we survey three top-down nanowire fabrication techniques which can be optimized according to specific applications. While they all share their dependency on the lithographic dimensions in a certain way, some of them offer the opportunity to reduce either the nanowire dimension, the pitch or both beyond this limit.…”

Section: Introductionmentioning

confidence: 99%

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Ben-Jamaa¹,

Gaillardon²,

Clermidy³

et al. 2011

sci adv mat

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Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properties, and some applications seem to be suitable for specific technologies. In this paper, we survey three nanowire technologies that yield nanowire arrays. All of them depend on the photolithography limit but they differ with respect to the processing and the device properties. We show the ability of the spacer technique to yield nanowires with a pitch below the photolithography limit. We introduce the nanowire crossbars in a pure CMOS process and extract the parasitics that affect nanowire crossbar circuits. Vertically stacked nanowires are also demonstrated with the deep reactive ion etching (DRIE) process. We link the surveyed processes to specific circuit architectures that are optimized for the considered technologies. A nanowire decoder for sub-lithographic nanowires is demonstrated with the smallest size compared to other competing technologies. Then an optimized crossbar multiplexer is presented, which takes into account the presence of parasitics. Finally, a general library of logic gates based on vertically stacked nanowires is evaluated showing a smaller area and a better performance than CMOS.

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“…Moreover, silicon is particularly interesting for molecular electronics because it can be terminated with organic moieties carrying wanted electrical properties (like reprogrammable molecules with two well separated conduction states) bonded to the silicon via environmentally robust Si-C bonds [15]. The MSPTs have succeeded in the preparation of silicon wire arrays with pitch p on the 10-nm length scale [16][17][18][19][20][21][22][23][24]: nanowires with width of 7 nm and arrays with p = 35 nm have actually been reported [17,18], whereas the most dense crossbar hitherto produced had a bit density of the order of 10 10 cm −2 [25]. The size to which a nanowire can be scaled down is manifestly limited by the appearance of quantum size effects.…”

Section: Silicon Nanowiresmentioning

confidence: 99%

Terascale integration via a redesign of the crossbar based on a vertical arrangement of poly-Si nanowires

Cerofolini

Ferri²,

Romano

et al. 2010

Semicond. Sci. Technol.

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The race of integrated-circuit technology toward high bit density has already brought to transistor densities of the order of 10 9 cm −2 , yet keeping conventional circuit layouts. Crossbar structures are widely believed to meet the requirements of high bit density along with sustainable interconnection complexity avoiding the dramatic cost increase of the manufacturing facilities required by advanced lithography. In this work we demonstrate the possibility of producing poly-Si nanowires preserving bulk electrical properties and nonetheless so dense as to allow cross-point density in excess of 10 11 cm −2 . This result could be achieved by organizing silicon nanowires in nearly vertical arrays.

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Multi-silicon ridge nanofabrication by repeated edge lithography

Cited by 27 publications

References 23 publications

Wafer-scale fabrication of nanoapertures using corner lithography

Wafer-scale fabrication of nanoapertures using corner lithography

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Terascale integration via a redesign of the crossbar based on a vertical arrangement of poly-Si nanowires

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