Multi-terabit ip lookup using parallel bidirectional pipelines

Abstract

To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi-pipeline architecture for multi-terabit rate IP lookup. The architecture consists of multiple bidirectional linear pipelines, where each pipeline stores part of a routing table.We address the challenges of realizing such a solution. Two mapping schemes with different granularity are proposed to balance the memory distribution over different pipelines as well as across different stages in each pipeline. Also, IP caching is adopted to facilitate processing multiple packets per clock cycle. Instead of using large reorder buffers and complex logic, a lightweight scheduler and several small output delay queues are developed to preserve the intra-flow packet order. Simulation experiments using real-life data show that the proposed 4-pipeline architecture can store a core routing table with over 200K unique routing prefixes in less than 2 MB of memory, and can achieve a high throughput of up to 18.75 billion packets per second (GPPS), i.e. 6 Tbps for minimum size (40 bytes) packets.

Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines

“…Our recent work [10] further extends the proposed architecture. By replacing the single-port SRAMs with dual-port SRAMs, we allow each pipeline to be traversed from two directions simultaneously.…”

Parallel IP lookup using multiple SRAM-based pipelines

“…Our recent work [10] further extends the proposed architecture. By replacing the single-port SRAMs with dualport SRAMs, we allow each pipeline to be traversed from two directions at the same time.…”

Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA

“…Such lookups are time critical and should be performed at wire speed. Meeting these tight requirements is extremely difſcult, if not impossible, on software platforms [10]. The kernel function of a router is to perform IP lookup.…”

“…Field Programmable Gate Arrays (FPGAs) have become a promising platform for high-speed next generation routers, mainly because of their reconſgurability and abundant parallelism [2], [3], [19]. They are used extensively as a hardware platform for multi-Gigabit packet processing engines [2], [10], [13], [18].…”

“…A TCAM update can possibly require an amount of time linear in the number of entries. The popular method used to update a tree/trie is using write bubbles [10], [12]. A write bubble traverses the pipeline the same way a packet traverses, either in forward or backward direction depending on the architecture.…”