Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power and Delay in Digital Circuits for Nano-Scale Technology

Khan, Waliur Rahman; Uzzal, Mohammad Mohiuddin

doi:10.1109/iciet48527.2019.9290556

Cited by 4 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…MTCMOS is technique in which the threshold voltages of the both NMOS and PMOS transistors are different , this technique is mainly is used to reduce the subthreshold leakage of MOS transistor [2][3] in standby mode (sleep mode) ,The MTCMOS technique can be operated in two modes High Threshold mode and Low threshold mode, in high Threshold mode it can be minimize the subthreshold [5] leakage and Low threshold mode can optimize the speed of the circuit.…”

Section: Mtcmos Techniquementioning

confidence: 99%

Low Power and High-Speed Multi-Threshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using EDA Tools

Banothu,

Surabhi,

Sridhar

et al. 2024

Preprint

View full text Add to dashboard Cite

The primary focus of Research VLSI Technology is to optimize power and Delay, so that a low power and High Speed Designs are obtained. The MTCMOS is one of the Such Promising CMOS Chip technology that uses transistors with multiple threshold voltages to optimize power and Delay. Subthreshold Leakage has brought down and achieved power optimization. In this article Multi threshold CMOS based Data Flip-Flop is Designed, analyzed and Validated on 90 nm Technology Node Using EDA Tools.

show abstract

Section: Mtcmos Techniquementioning

confidence: 99%

Low Power and High-Speed Multi-Threshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using EDA Tools

Banothu,

Surabhi,

Sridhar

et al. 2024

Preprint

View full text Add to dashboard Cite

show abstract

“…Here is the figure 4 that represents the situation they test. Also, there is a new idea about to decrease the delay for CMOS in VLSI circuits without large changes in power dissipation, which is called Multi-Threshold CMOS [9]. It discusses the usage of High threshold CMOS devices for low threshold requirements, and the usage of Low threshold CMOS devices for high threshold requirements.…”

Section: Optimization Directionmentioning

confidence: 99%

Third generation semiconductor device research: Optimizing CMOS and HEMT designs

Chen,

Jing,

Mou

2024

ACE

View full text Add to dashboard Cite

The third-generation semiconductor device known as High Electron Mobility Transistors (HEMT) has found extensive applications in high-frequency and high-speed electronic systems. Its widespread usage in critical technologies such as radio telescopes, satellite broadcast receivers, and cellular base stations has established HEMT as a foundational technology underpinning our information and communication society. This paper provides an in-depth exploration of these semiconductor advancements. Firstly, the paper utilizes the CMOS inverter as a representative example to elucidate the fundamental structure of Complementary Metal-Oxide-Semiconductor (CMOS) technology. Additionally, it employs Gallium Arsenide (GaAs) HEMT as an illustrative instance to expound upon the architecture of HEMT devices. Furthermore, the paper delves into the optimization of CMOS technology, focusing on topics such as Multi-Threshold CMOS and the impact of the Width/Length (W/L) ratio. These discussions shed light on ways to enhance the performance of CMOS-based components. Additionally, the paper explores strategies to optimize HEMT devices, including the introduction of carbon doping and the application of the Grey-Wolf optimization technique. These approaches are critical in achieving higher efficiency and performance in HEMT-based applications.

show abstract

Enhancing Design Robustness Accounting for Process Variations of Multi-transistor Designs

Mandal

2024

2024 8th IEEE Electron Devices Technology &Amp;amp; Manufacturing Conference (EDTM)

View full text Add to dashboard Cite

Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power and Delay in Digital Circuits for Nano-Scale Technology

Cited by 4 publications

References 9 publications

Low Power and High-Speed Multi-Threshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using EDA Tools

Low Power and High-Speed Multi-Threshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using EDA Tools

Third generation semiconductor device research: Optimizing CMOS and HEMT designs

Enhancing Design Robustness Accounting for Process Variations of Multi-transistor Designs

Contact Info

Product

Resources

About