Multi-Vth technique based on potential critical paths for NBTI effect and leakage tradeoff

SummaryAs a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively.

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Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

Bhattacharjee

Sahu

Pradhan

2021

Circuit Theory & Apps

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Multi-Vth technique based on potential critical paths for NBTI effect and leakage tradeoff

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References 12 publications

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

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