Multibit $\Sigma$–$\Delta$ PWM Digital Controller IC for DC–DC Converters Operating at Switching Frequencies Beyond 10 MHz

Digital Multi-Bit Sigma-Delta Controller for Synchronous Buck DC-DC Converter

“…DPWM base on sigma-delta modulator consists of a low-resolution low-power DPWM capable of operating at high switching frequencies and a sigma-delta modulator, which improves effective resolution of the core DPWM. The sigma-delta operation is based on the well known noise-shaping concept widely used in analog-to-digital and digital-to-analog converters [8]- [12]. Over several switching cycles, the modulator varies the low-resolution input of the core DPWM, between few possible values to achieve a high-resolution average duty ratio value.…”

“…At higher switching frequencies the analog controllers take much less power, and consequently are more suitable solution, even though they do not posses most of the abovementioned features [5], [6]. One of the main limitations to maximum switching frequency at which digital controllers can be effectively used in low-power applications is the power consumption of digital pulse width modulator (DPWM).…”

“…It is designed for higher power DC-DC converters, where the power consumption of the controller is not so crucial. In addition at maximum switching frequency the resolution of the DPWM is low [1], [6], [7], [8].…”

ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

“…The use of constant-frequency pulse-width modulation is widespread in switching power converters, although a sigma-delta scheme for modulation [11][12][13][14][15] and varying switching frequency schemes, such as sliding-mode and hysteretic control [16][17][18][19][20][21][22][23][24][25][26], for control can also be used. The pulse width modulation (PWM) principle is widely used in power electronics applications for controlling power converters (DC-DC, DC-AC, etc.)…”

“…In the first group of architectures an attempt has been made to obtain the minimum time step in the DPWM by changing the hardware architecture of the DPWM. In the second group of architectures the effective duty cycle resolution has been increased using a software approach that changes the pattern used in the generation of the output signal i.e Digital dither [9,51,58,59] and sigma-delta [11][12][13]. A new set of architectures has been presented to reduce the minimum time step of DPWM by using the FPGA's advance resources and hybrid architectures with software approach.…”