Multicore soft error rate stabilization using adaptive dual modular redundancy

Vadlamani, Ramakrishna; Zhao, Jia; Burleson, Wayne; Tessier, Russell

doi:10.1109/date.2010.5457242

Cited by 67 publications

(34 citation statements)

References 13 publications

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“…These errors can damage the correct software execution by producing erroneous results if the computation is completed, or by preventing the execution of the application by causing exceptions, interrupts, abnormal terminations or applications hang-up. Nevertheless, the software stack can also play an important role in masking errors, introducing a further error masking effect (Software Vulnerability Factor -SVF), which may further improve the system reliability [39][40][41][42][43][44][45][46].…”

Section: A Cross-layer Approach For System Reliability Evaluationmentioning

confidence: 99%

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Vallero

Tselonis

Foutris

et al. 2015

Microprocessors and Microsystems

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International audienceAdvanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market

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Section: A Cross-layer Approach For System Reliability Evaluationmentioning

confidence: 99%

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Vallero

Tselonis

Foutris

et al. 2015

Microprocessors and Microsystems

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“…Some works, e.g. [35], [36], [37] have proposed multi-core architectures that exploit redundancy at different levels of abstraction to target low-energy consumption and reliability. [35] has proposed an adaptive multicore architecture that selectively adjusts pipeline-level redundancy to satisfy reliability target with low energy consumption.…”

Section: Related Workmentioning

confidence: 99%

“…[36] has proposed a customizable chip-level redundancy technique for multi-core systems that utilizes power efficient hardware fault-detection mechanisms along with forward recovery to reduce overheads in case of fault-free executions. [37] has considered the effects of DVS on the soft error rate and proposed a flexible dual modular redundancy (DMR) mechanism that selectively enables per-core DMR to increase reliability. However, these works require hardware modification or redesign, and hence, cannot be used by the current commercial-offthe-shelf processors, while our proposed technique is general and can be exploited by any multi-core processor that supports DVS.…”

Section: Related Workmentioning

confidence: 99%

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Salehi

Ejlali

Al-Hashimi

2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multicore systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered: i) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving, ii) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energymanagement technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29% energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work.

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“…[4] Chip Multiprocessors or CMPs are inherently good for reliability due to the availability of many cores, on which redundant computations can be performed for error detection, and/or correction. Many redundancy based techniques, at various levels of design space abstraction, based on Dual Modular Redundancy (DMR) [5], Triple Modular Redundancy (TMR) [6], and checkpointing [7] have been proposed to enable error detection and correction in CMPs. Reunion [8] is one promising redundancy based multi-core architectures that achieves error resilience with low performance overhead.…”

Section: Introductionmentioning

confidence: 99%

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Jeyapaul

Hong

Rhisheekesan

et al. 2011

2011 International Conference on Parallel Processing

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Abstract-Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. In this work, we propose a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. We also perform cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, our UnSync architecture reduces power consumption by 34.5% and improves performance by up to 20% with 13.3% less area overhead, when compared to Reunion architecture for the same level of reliability achieved.

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Multicore soft error rate stabilization using adaptive dual modular redundancy

Cited by 67 publications

References 13 publications

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

UnSync: A Soft Error Resilient Redundant Multicore Architecture

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