Multifunctional integrated photonic switches

Abstract

Abstract-Traditional optical-electronic-optical (o-e-o) conversion in today's optical networks requires cascading separately packaged electronic and optoelectronic chips and propagating high-speed electrical signals through and between these discrete modules. This increases the packaging and component costs, size, power consumption, and heat dissipation. As a remedy, we introduce a novel, chip-scale photonic switching architecture that operates by confining high-speed electrical signals in a compact optoelectronic chip and provides multiple network functions on such a single chip. This new technology features low optical and electrical power consumption, small installation space, high-speed operation, two-dimensional scalability, and remote electrical configurability.In this paper, we present both theoretical and experimental discussion of our monolithically integrated photonic switches that incorporate quantum-well waveguide modulators directly driven by on-chip surface-illuminated photodetectors. These switches can be conveniently arrayed two-dimensionally on a single chip to realize a number of network functions. Of those, we have experimentally demonstrated arbitrary wavelength conversion across 45 nm and dual-wavelength broadcasting over 20 nm, both spanning the telecommunication center band (1530-1565 nm) at switching speeds up to 2.5 Gb/s. Our theoretical calculations predict the capability of achieving optical switching at rates in excess of 10 Gb/s using milliwatt-level optical and electrical switching powers.

Violet to deep-ultraviolet InGaN∕GaN and GaN∕AlGaN quantum structures for UV electroabsorption modulators

“…[18][19][20] We use RIE to etch down to the middle of n layer to define device mesas, as illustrated in Fig. 1.…”

Self-aligned via and trench for metal contact in III-V semiconductor devices

“…We have experimentally demonstrated working waveguide EAM devices with a 1000 Å thick Si 3 N 4 sidewall protection. 5,6 Our method described above, whether employed as it is or in combination with another method, 7 has proven to be successful in achieving wafer-level integration of InP-based integrated photonic switch devices. 5,6 Although we have not applied this method to devices implemented in other III-V material systems, such as GaAs, we believe that the method should be applicable to them in principle.…”

“…5,6 Our method described above, whether employed as it is or in combination with another method, 7 has proven to be successful in achieving wafer-level integration of InP-based integrated photonic switch devices. 5,6 Although we have not applied this method to devices implemented in other III-V material systems, such as GaAs, we believe that the method should be applicable to them in principle. Furthermore, if the device sizes call for even smaller via ͑and trench͒ formation than the ones presented here, it should still be possible to scale the openings proportionally down, even to nanometer feature sizes in principle, as long as ͑i͒ the wet etch removal of nanometer size oxide hard mask ͑or InP sacrificial layer, for that matter͒ is still possible and ͑ii͒ the Si 3 N 4 protection layer does not induce any adverse effect due to its minimum thickness requirements.…”

“…In so doing, difficulties may arise, especially in wafer-level integrated processing, due to nonuniformities of the spin-on polymer thickness and the etch rate of the polymer across the wafer. Additionally, for example, in the case of monolithic integration, any device height variation due to epitaxial regrowth processes 5,6 can also lead to the nonplanarization of the polymer on devices across an integrated chip and/or the whole wafer. In a͒ Author to whom correspondence should be addressed; electronic mail: jun.f.zheng@intel.com such cases, the exposure of device sidewalls becomes an unavoidable problem in any attempt to clear the polymer from all of the device tops.…”

Photovoltaic nanocrystal scintillators hybridized on Si solar cells for enhanced conversion efficiency in UV

“…The reasons for blending nanocrystals in a very small amount of polymeric solution include obtaining a high film quality and a sharp edge in the optical absorption spectra of the resulting nanocrystal-polymer thin film. To fabricate our samples, we use standard fabrication techniques similar to those developed and described in our previous optoelectronics device work [17][18][19][20][32][33][34][35]. We prepare the nanocrystal-polymer films on our samples on the hot plate (at 50 °C) to achieve uniform films.…”