Multilayered ALD HfAlO_x and HfO₂ for High-Quality Gate Stacks

Abstract

This paper has demonstrated a high-quality HfO 2based gate stack by depositing atomic-layer-deposited HfAlO x along with HfO 2 in a layered structure. In order to get a multifold enhancement of the gate stack quality, both Al percentage and distribution were observed by varying the HfAlO x layer thickness and its location in the gate stack. It was found that < 2% Al/(Al + Hf)% incorporation can result in up to 18% reduction in the average EOT along with up to 41% reduction in the gate leakage current, as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increased the interface state density D it . When devices were stressed in the gate injection mode at a constant voltage stress, the dielectrics with Al/(Hf+Al)% < 2% showed resistance to stressinduced flatband voltage shift ΔV F B , and stress-induced leakage current. The time-dependent dielectric breakdown characteristics showed a higher charge to breakdown and an increase in the extracted Weibull slope β, which further confirms an enhanced dielectric reliability for devices with < 2% Al/(Al + Hf)%. Index Terms-Equivalent oxide thickness (EOT), HfAlO x , interface state density (D it ), stress-induced flatband voltage shift (ΔV F B ), stress-induced leakage current (SILC), time-dependent dielectric breakdown (TDDB).

Ferroelectric Polarization Enhancement in Hafnium-Based Oxides Through Capping Layer Engineering

“…It can be clearly observed that the trapping level gradually changes from 0.66 eV to 0.77 eV with increasing the CL thickness up to 2nm. The deeper trapping level of 0.77 eV is mainly ascribed to the effect of AlO x CL, which not only reduces the shallow traps near TaN/HfZrO x interface [27], [28], but also enhances the thermal stability of HfZrO x MFM capacitor. Therefore, the AlO x CL effectively improves interface quality to eliminate the interface shallow traps, possibly causing charge trapping/detrapping and domain wall pining during ferroelectric switching.…”

Further Cost Reduction of Battery Manufacturing

“…The reliability of semiconductor products has helped this industry to enjoy stable growth. The reliabilities of transistors and their gates are treated with high importance in semiconductor fabrication [35]. Now, the reliability of battery and lifetime modeling is also drawing attention [36].…”

“…With the desired goal of reducing cell-to-cell variation, the focus has to be on the contributing factors that are responsible for the process variation. Analytical expression presented by Sikha et al [56], and the resistance and capacitance models of Shin et al [35] provide insight into the battery performance. This model can be used to further breakdown and identify the key contributors to cell properties, as shown in Figure 5 [38].…”

Intersection behavior of the current–voltage (I–V) characteristics of the (Au/Ni)/HfAlO3/n-Si (MIS) structure depends on the lighting intensity

“…These properties cause a significant increase in the leakage current if HfO 2 films are incorporated in a high-temperature MIS system. To increase the crystallization temperature and enhance the electrical properties of HfO 2 , it can be converted to alloy HfAlO x (hafnium aluminum) using aluminum oxide (Al 2 O 3 ) intermixed [19][20][21]. Furthermore, the integration of the Al into HfO 2 causes an increase in its dielectric constant and bandgap as well as decreases its hysteresis and charging defects.…”