Multilevel charge storage in silicon nanocrystal multilayers

Abstract

Evidence of a thermally stimulated charge transfer mechanism and interface defect formation in metal-oxidesemiconductor structures with germanium nanocrystals

Electrical transport mechanisms in ensembles of silicon quantum dots

“…This is of course since we have isolated QDs and the communication between the QDs can only be by that mechanism. This is to be contrasted with the common 2D (sandwich-MOS) configuration of Si QDs where only one QD is involved in the transport, and the injection of a carrier from the electrodes may involve a Fowler-Nordheim phenomena [35,36]. For larger x values we expect intra-cluster migration and intercluster tunneling.…”

Charge trapping and de‐trapping in Si‐nanoparticles embedded in silicon oxide films

“…[1][2][3][5][6][7]. However, compatible techniques with complementary metal oxide semiconductor (CMOS) are preferred.…”

“…Light emitting devices (LED) [1], single electron memories, [2] and UV photodetectors [3] are some of their interesting demonstrated devices. These potential applications have recently been of great interest for many researchers.…”

Silicon Oxide Films Containing Amorphous or Crystalline Silicon Nanodots for Device Applications

“…The insulator of such MIS structure normally consists of three layers (Dimitrakis et al, 2005;Tiwari et al, 1996;Tsoi et al, 2005): (i) ultra thin tunnel SiO 2 layer grown on the crystalline Si wafer followed by (ii) composite layer of Si nanocrystals (NCs) in a SiO 2 matrix (nc-Si-SiO 2 ) and (iii) control SiO 2 layer, which insulates the NCs from the control gate. The middle nc-Si-SiO 2 layer has been mostly prepared by ion implantation of Si in thermal SiO 2 and subsequent annealing at high temperature ( 900 0 ) (Normand et al, 2004 and references therein;Carreras et al, 2005;Ng et al, 2006a), by applying some chemical vapor deposition (CVD) technique for Si nanocrystals fabrication and subsequent CVD deposition of silicon dioxide (Lombardo et al, 2004;Oda et al, 2005;Rao et al, 2004), by deposition of a ultra thin amorphous Si layer and a subsequent oxidation of this layer at a high temperature (Kouvatsos et al, 2003;Tsoi et al, 2005) or by thermal evaporation of SiO powder under selected oxygen pressure (Lu et al, 2005(Lu et al, , 2006.…”

“…It uses multiple dielectric stacks to enhance field-sensitivity and thus to allow for shorter writing/erasing times and/or lower operating voltages than single SiO 2 tunnel oxide without altering the ten-year data retention constraint. Experiments on memory structures containing one-three Si NC layers prepared by evaporation of SiO powder and layer by layer growth (Lu et al, 2005(Lu et al, , 2006 have shown that in structures with two or three NC layers two or three different saturation voltages were obtained with increasing bias related to charge injection to and capture at the first, second, or third NC layer (Lu et al, 2005). Charge captured in the first layer yielded a memory window width of about 2.5 V, charge captured in the second NC layer yielded an additional flat-band voltage shift of about 2.5 V, while charge captured in the third layer yielded an additional shift of about 1.5 V. It has been observed that the multilayer storage in memory structures prepared by different deposition methods yielded very good retention, as well (Han et al, 2007;Lu et al, 2005;Nassiopoulou et al, 2009).…”