Multilevel optimization for large-scale circuit placement

Chan, Tony F.; Cong, Jason; Kong, Tianming; Shinnerl, Joseph R.

doi:10.1109/iccad.2000.896469

Cited by 109 publications

(128 citation statements)

References 20 publications

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“…• mPL: mPL [16] is a multilevel placement algorithm. It uses nonlinear programming to handle the non-overlapping constraints on the coarsest level, then uses Goto-based [38] relaxation in subsequent refinement stages.…”

Section: Studies Of Placement Algorithms 31 Optimality and Scalabilimentioning

confidence: 99%

“…The iterative force-directed method [15] outperformed Gordian-L in 1998 by an average of 6%. The mPL placer [16] runs 10x faster than Gordian-L with a penalty of wirelength increase of 10%. The latest developments in placement algorithms in the past three years, including Capo [17], Dragon [18], Mongrel [19], and mPG [20] vary mostly in runtime.…”

Section: Introductionmentioning

confidence: 99%

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Optimality, scalability and stability study of partitioning and placement algorithms

Cong

Romesis

Xie

2003

Proceedings of the 2003 International Symposium on Physical Design

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This paper studies the optimality, scalability and stability of state-of-the-art partitioning and placement algorithms. We present algorithms to construct two classes of benchmarks, one for partitioning and the other for placement, which have known upper bounds of their optimal solutions, and can match any given net distribution vector. Using these partitioning and placement benchmarks, we studied the optimality of state-ofthe-art algorithms by comparing their solutions with the upper bounds of the optimal solutions, and their scalability and stability by varying the sizes and characteristics of the benchmarks. The conclusions from this study are: 1) State-ofthe-art, multilevel two way partitioning algorithms scale very well and are able to find solutions very close to the upper bounds of the optimal solutions of our benchmarks. This suggests that existing circuit partitioning techniques are fairly mature. There is not much room for improvement for cutsize minimization for problems of the current sizes. Multiway partitioning algorithms, on the other hand, do not perform that well. Their results can be up to 18% worse than our estimated upper bounds. 2) The state-of-the-art placement algorithms produce significantly inferior results compared with the estimated optimal solutions. There is still significant room for improvement in circuit placement. 3) Existing placement algorithms are not stable. Their effectiveness varies considerably depending on the characteristics of the benchmarks. New hybrid techniques are probably needed for future generation placement engines that are more scalable and stable.

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Section: Studies Of Placement Algorithms 31 Optimality and Scalabilimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimality, scalability and stability study of partitioning and placement algorithms

Cong

Romesis

Xie

2003

Proceedings of the 2003 International Symposium on Physical Design

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“…MB*-tree is inspired by the success of the multilevel framework in graph/circuit partitioning such as Chaco [10], hMetis [12], and ML [2], placement such as MPL [4], £ This work was partially supported by the National Science Council of Taiwan by Grant No. NSC-91-2215-E-002-038.…”

Section: Introductionmentioning

confidence: 99%

Multilevel floorplanning/placement for large-scale modules using B*-trees

Lee¹,

Chang

Hsu

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.

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“…Existing solutions often require the designer to manually partition a circuit which results in a much more complex design flow and leads to sub-optimal results during placement. Effective approaches using a multi-level clustering have been proposed in [1,2,3]. However, these existing approaches only reflect connectivity properties and not the functionality of the netlist.…”

Section: Introductionmentioning

confidence: 99%

Congestion aware layout driven logic synthesis

Kutzschebauch¹,

Stok²

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

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In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.

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Multilevel optimization for large-scale circuit placement

Cited by 109 publications

References 20 publications

Optimality, scalability and stability study of partitioning and placement algorithms

Optimality, scalability and stability study of partitioning and placement algorithms

Multilevel floorplanning/placement for large-scale modules using B*-trees

Congestion aware layout driven logic synthesis

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