Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

Healy, Michael B.; Vittes, M.; Ekpanyapong, Mongkol; Ballapuram, Chinnakrishnan S.; Lim, Sung Kyu; Lee, H.-H.S.; Loh, Gabriel H.

doi:10.1109/tcad.2006.883925

Cited by 84 publications

(52 citation statements)

References 37 publications

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“…In the context of 3D MPSoCs, temperature-aware floorplanning has also been extended by including the interlayer thermal dissipation and interconnect characteristics [102,[104][105][106]. For example, initial work has been proposed [107] for temperatureaware microarchitectural floorplanning.…”

Section: Design-time Power and Thermal Optimizationsmentioning

confidence: 99%

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Kim

Sabry

Ruggiero

et al. 2015

Handbook on Data Centers

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Section: Design-time Power and Thermal Optimizationsmentioning

confidence: 99%

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Kim

Sabry

Ruggiero

et al. 2015

Handbook on Data Centers

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“…[27,28] propose invoking energy saving techniques when the temperature exceeds a predefined threshold. [5] proposes a performance and thermal aware floorplanning algorithm to estimate power and thermal effects for 2D and 3D architectures using an automated floor-planner with iterative simulations. To our knowledge, little research has been completed so far in developing accurate and informative analytical methods to forecast complex thermal spatial behavior of emerging 3D multi-core processors at early architecture design stage.…”

Section: Fig 14 the Roles Of Input Parametersmentioning

confidence: 99%

“…In addition, 3D offers the opportunity of binding dies, which are implemented with different techniques to enable integrating heterogeneous active layers for new system architectures. Leveraging 3D die stacking technologies to build uni-/multi-core processors has drawn an increased attention to both chip design industry and research community [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

“…Previous studies [5,6] show that 3D chip temperature is affected by factors such as configuration and floor-plan of microarchitectural components. For example, instead of putting hot components together, thermal-aware floor-planning places the hot components by cooler components, reducing the global temperature.…”

Section: Introductionmentioning

confidence: 99%

“…For example, instead of putting hot components together, thermal-aware floor-planning places the hot components by cooler components, reducing the global temperature. Thermal-aware floor-planning [5] uses intensive and iterative simulations to estimate the thermal effect of microarchitecture components at early architectural design stage. However, using detailed yet slow cycle-level simulations to explore thermal effects across large design space of 3D multi-core processors is very expensive in terms of time and cost.…”

Section: Introductionmentioning

confidence: 99%

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Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models

Cho

Zhang

2009

Computer Performance Evaluation and Benchmarking

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Abstract. -This paper presents novel 2D geospatial-based predictive models for exploring the complex thermal spatial behavior of three-dimensional (3D) die stacked multi-core processors at the early design stage. Unlike other analytical techniques, our predictive models can forecast the location, size and temperature of thermal hotspots. We evaluate the efficiency of using the models for predicting within-die and cross-dies thermal spatial characteristics of 3D multi-core architectures with widely varied design choices (e.g. microarchitecture, floor-plan and packaging). Our results show the models achieve high accuracy while maintaining low complexity and computation overhead.

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Multiobjective Optimization Techniques

Agastra

Pelosi

Selleri

et al. 2014

Wiley Encyclopedia of Electrical and Electronics Engineering

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Designing an electronic system is an engineering task bound to the satisfaction of a given set of requirements. If it is possible to express the compliance of the system to the requirements in a mathematical form giving a measure of how much a given system is far from compliance, then it would be possible to obtain the desired performances by seeking for the minimum of such a function. Seeking the minimum of a function is a daunting task to which a whole branch of mathematics, optimization, is devoted. In the case in which the design must comply to several requirements, it is usually more practical and interesting to define a set of functions to be minimized altogether. In this case the search for an optimal point, or a set of points, can be performed by applying a multi‐objective optimization technique. This chapter will investigate popular multi‐objective optimization techniques, giving both their basics and describing recent advancements. For the selected techniques, performances over a set of benchmarks will be presented, as well as results over relevant electronic engineering problems.

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Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

Cited by 84 publications

References 37 publications

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models

Multiobjective Optimization Techniques

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