Multiphase digitally controlled oscillator for future 5G phased arrays in 90 nm CMOS

Devos, Arnout; Vigilante, Marco; Reynaert, Patrick

doi:10.1109/norchip.2016.7792882

Cited by 4 publications

(2 citation statements)

References 6 publications

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“…Usually LC tank oscillators are used to achieve low phase noise. LC tank DCOs and the oscillator's component of DCO noise are widely researched and discussed [18][19][20], therefore, here the focus will be on the quantization component of DCO noise. It can be seen from Figure 4 that ∆Σ quantization and noise shaping improves DCO's quantization noise by more than 40 dBc/Hz at small frequency offsets from the carrier (in-band).…”

Section: Requirements For Blocks Of All-digital Multiband Frequency Smentioning

confidence: 99%

Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

Jurgo

Navickas

2018

Electronics

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In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.

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Section: Requirements For Blocks Of All-digital Multiband Frequency Smentioning

confidence: 99%

Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

Jurgo

Navickas

2018

Electronics

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“…It is well-known that the quality factor (Q) degradation of tuning varactors in mmW RTWOs leads to worse PN in the thermal noise (1/ f 2 ) region [9], [14]. Many techniques have been introduced to mitigate such degradation, such as inductive loading [11], using an array of coupled oscillators [6], [9], and combining standing-wave and traveling-wave modes (hybrid RTWO) as devised in [9] and [10].…”

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confidence: 99%

A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator

Shehata

Keaveney

Staszewski

2021

IEEE J. Solid-State Circuits

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A rotary traveling-wave oscillator (RTWO) has an ability to generate multiple phases at millimeter-wave (mmW) frequencies while achieving low phase noise (PN). Unfortunately, due to the practically unavoidable transmission line (TL) dispersion, which causes the higher-order harmonics to travel faster than the fundamental, RTWOs suffer from flicker noise upconversion. In this article, we propose a "distributed stubs" technique to mitigate this mechanism in which tuning capacitors placed on the TL stubs away from the maintaining amplifiers will slow down the travel speed of higher-order harmonics relative to the fundamental, thus lowering the phase shifts due to the TL dispersion. We further provide a comprehensive analysis of the flicker noise upconversion mechanism due to the TL dispersion. The proposed 26.2-30-GHz RTWO is implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS with eight differential phases. At 30 GHz, it achieves PN of −107.6 and −128.9 dBc/Hz at 1-and 10-MHz offsets, respectively. This translates into figures-of-merit (FoMs) of 184.2 and 185.4 dB, respectively, for a single phase. The proposed architecture consumes 20 mW from 0.8-V supply. It achieves a flicker PN corner of 180 kHz, which is an orderof-magnitude better than currently achievable by state-of-the-art mmW RTWOs.

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