Multiple beam inspection (MBI) for 7nm node and beyond: technologies and applications

Long, Eric; Chou, Kevin; Ebert, Martin; Liu, Xuedong; Ren, Weiming; Hu, Xuerang; Maassen, Martijn; Yin, Weihua; Chen, Aiden; Wang, Fei; Patterson, Oliver D.

doi:10.1117/12.2515272

Cited by 5 publications

(2 citation statements)

References 5 publications

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“…However, a few focus steps might be needed because the reduction in spherical aberration results in a small depth of field. SEM has also been used to construct the 3D structure features by using the multiple SEM beams [391,392] and detecting the backscattered electrons from multiple primary beam energies. This method is much faster than that of TEM techniques.…”

Section: Scanning Electron Microscopy (Sem)mentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Scanning Electron Microscopy (Sem)mentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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show abstract

“…Two key factors in MI are throughput and accuracy. To accelerate MI and improve throughput, new technologies such as multi-beam inspection [1] and massive overlay measurement [2][3] have been developed. For accuracy enhancement, EUV imaging [4], multi-angle ellipsometry [5], fluorescence imaging [6], ptychography [7], and microsphere-assisted hyperspectral imaging [8] have been developed.…”

Section: Introductionmentioning

confidence: 99%

Interactive image annotation and AI-assisted segmentation of TEM images for automatic CD measurement

Kim,

Lee,

Yim

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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As the semiconductor structures become increasingly miniaturized and complex, the process of measuring and analyzing the structure using a microscope becomes crucial. High-resolution transmission electron microscope (TEM) images are widely used, but they are expensive to acquire and analyze. If the region and boundary of the material in the TEM image can be automatically segmented, the measurement cost will be reduced. We proposed a method to generate a segmentation label for a TEM image using a deep learning model that performs segmentation based on weak supervision and active learning. The proposed method achieved an accuracy of 98% in 10% of the time compared to the manual method. This approach will reduce the cost of high-resolution TEM image analysis and accelerate the semiconductor device development process.

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Surface Contaminants and Surface Cleanliness Levels

Kohli

2022

Surfactants in Precision Cleaning

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Multiple beam inspection (MBI) for 7nm node and beyond: technologies and applications

Cited by 5 publications

References 5 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Interactive image annotation and AI-assisted segmentation of TEM images for automatic CD measurement

Surface Contaminants and Surface Cleanliness Levels

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