Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications

Banerjee, Arijit; Kamineni, Sumanth; Calhoun, Benton H.

doi:10.1145/3218603.3218628

Cited by 3 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a result, this method is likewise not appropriate for low voltage operation. In addition to this, attempts were also made by B. Wang, et al [19] proposing ultra-low voltage 9T SRAM cell (9T UV SRAM), M. H. Tu, et al [20], A. Banerjee, S. Kamineni and B. H. Calhoun [21] etc. to reduce the static power dissipation and for improvement of read/write operation.…”

Section: Related Workmentioning

confidence: 99%

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat,

Kumar

2024

Preprint

View full text Add to dashboard Cite

Static random access memory (SRAM) is the typical memory for very large scale integrated (VLSI) circuits. A major reason for this is the high speed operation for SRAM in comparison to its previous counterparts, a major trade off for the circuit is its high power consumption. With the growing importance of memory architectures, it is crucial to lower the power consumption of SRAM cells. This major goal of this paper is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). SRAM is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The paper is organized into the following sections: 1. Introduction, Section 2 describes related work. The suggested work is explained in section 3, while the results and discussion are included in section 4. The results for all the sections are concluded in section 5 conclusions.

show abstract

Section: Related Workmentioning

confidence: 99%

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat,

Kumar

2024

Preprint

View full text Add to dashboard Cite

show abstract

“…Authors in [18] show the use of dual write and read PAs that reduces the V MIN and improves the yield. Moreover, authors in [19] discussed some appropriate combination of PAs (CPAs) that could lower the V MIN further for FinFETs at near-subthreshold supplies, such as a combination of negative bitline with boosting the V DD , etc. One could employ different CPAs based on V MIN lowering application needs.…”

Section: Write and Read Peripheral Assist Techniques For Low-v Min Apmentioning

confidence: 99%

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Banerjee¹

2018

Green Electronics

Self Cite

View full text Add to dashboard Cite

Internet of Things (IoT) devices such as wearable health monitors, augmented reality goggles, home automation, smart appliances, etc. are a trending topic of research. Various IoT products are thriving in the current electronics market. The IoT application needs such as portability, form factor, weight, etc. dictate the features of such devices. Small, portable, and lightweight IoT devices limit the usage of the primary energy source to a smaller rechargeable or non-rechargeable battery. As battery life and replacement time are critical issues in battery-operated or partially energy-harvested IoT devices, ultralow-power (ULP) system on chips (SoC) are becoming a widespread solution of chip makers' choice. Such ULP SoC requires both logic and the embedded static random access memory (SRAM) in the processor to operate at very low supply voltages. With technology scaling for bulk and FinFET devices, logic has demonstrated to operate at low minimum operating voltages (V MIN). However, due to process and temperature variation, SRAMs have higher V MIN in scaled processes that become a huge problem in designing ULP SoC cores. This chapter discusses the latest published circuits and architecture techniques to minimize the SRAM V MIN for scaled bulk and FinFET technologies and improve battery life for ULP IoT applications.

show abstract

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

Mishra

Mankali

Kandpal

et al. 2021

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

show abstract

Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications

Cited by 3 publications

References 7 publications

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

Contact Info

Product

Resources

About