Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs

Nasiri, Ehsan; Shaikh, Javeed; Pereira, André Hahn; Betz, Vaughn

doi:10.1109/tvlsi.2015.2478280

Cited by 28 publications

(3 citation statements)

References 15 publications

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“…The first device (RAD1), illustrated in Fig. 11(a), consists of two identical FPGA fabrics using 2.5D chip integration [46] where the NoC links are the only wires crossing from one fabric to another through a passive interposer. The second one (RAD2) in Fig.…”

Section: A Experimental Setup and Methodologymentioning

confidence: 99%

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

2022

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In recent years, field-programmable gate arrays (FPGAs) have been increasingly deployed in datacenters as programmable accelerators that can offer software-like flexibility and custom-hardwarelike efficiency for key datacenter workloads. To improve the efficiency of FPGAs for these new datacenter use cases and data-intensive applications, a new class of reconfigurable acceleration devices (RADs) is emerging. In these devices, the FPGA fine-grained reconfigurable fabric is a component of a bigger monolithic or multi-die system-in-package that can incorporate general-purpose software-programmable cores, domain-specialized accelerator blocks, and high-performance networks-on-chip (NoCs) for efficient communication between these system components. The integration of all these components in a RAD results in a huge design space and requires re-thinking the implementation of applications that need to be migrated from conventional FPGAs to these novel devices. In this work, we introduce RAD-Sim, an architecture simulator that allows rapid design space exploration for RADs and facilitates the study of complex interactions between their various components. We also present a case study that highlights the utility of RAD-Sim in re-designing applications for these novel RADs by mapping a state-of-the-art deep learning (DL) inference FPGA overlay to different RAD instances. Our case study illustrates how RAD-Sim can capture a wide variety of reconfigurable architectures, from conventional FPGAs to devices augmented with hard NoCs, specialized matrix-vector blocks, and 3D-stacked multi-die devices. In addition, we show that our tool can help architects evaluate the effect of specific RAD architecture parameters on end-to-end workload performance. Through RAD-Sim, we also show that novel RADs can potentially achieve 2.6× better performance on average compared to conventional FPGAs in the key DL application domain.INDEX TERMS deep learning, field-programmable gate arrays, hardware acceleration, network-on-chip, reconfigurable computing

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Section: A Experimental Setup and Methodologymentioning

confidence: 99%

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

2022

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“…Previous work on design partitioning for multi-SLR FPGAs is mostly focused on timing closure optimization. References [19,38] make changes to the VPR place and route tool to minimize the number of wires crossing between SLRs in an effort to minimize timing impact. References [34,35] further separate the placement flow into a coarse partitioning stage, which minimizes SLR crossings and a detail placement stage for each partition independently.…”

Section: Partitioning Designs For Single-node Multi-slr Fpgasmentioning

confidence: 99%

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

Alonso

Petrică

Ruiz

et al. 2021

ACM Trans. Reconfigurable Technol. Syst.

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Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN layers and layers to individual FPGA dies to maximize the total performance of the multi-FPGA system. In the resulting Elastic-DF mapping, the accelerator may be instantiated multiple times, and each instance may be segmented across multiple FPGAs transparently, whereby the segments communicate peer-to-peer through 100 Gbps Ethernet FPGA infrastructure, without host involvement. When applied to ResNet-50, Elastic-DF provides a 44% latency decrease on Alveo U280. For MobileNetV1 on Alveo U200 and U280, Elastic-DF enables a 78% throughput increase, eliminating the performance difference between these cards and the larger Alveo U250. Elastic-DF also increases operating frequency in all our experiments, on average by over 20%. Elastic-DF therefore increases performance portability between different sizes of FPGA and increases the critical throughput per cost metric of datacenter inference.

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“…Some research has been conducted to parallelize designs automatically [4], [5], [6], [7]. They partitioned a dataflow into several blocks and distribute them among nodes considering data dependency and communication.…”

Section: Introductionmentioning

confidence: 99%

Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication

Miyasaka

Goda

Mittal

et al. 2020

IPSJ Transactions on System LSI Design Methodology

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Recently, there have been more chances to calculate matrix-vector multiplication due to the growing use of the neural network. We have proposed the method to automatically synthesize the optimum parallel algorithm for the given environment and synthesized an algorithm for matrix-vector multiplication of a specific size matrix with 4 nodes connected in a oneway ring. This paper proposes a method to generalize the synthesized algorithm to deal with any size matrix. We generalized the synthesized algorithm for the 32 × 32 matrix to calculate N × N matrix-vector multiplication.

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Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs

Cited by 28 publications

References 15 publications

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication

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