Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation

Lin, Yung‐Chieh; Li, Feng; Cheng, Kwang-Ting

doi:10.1109/tcad.2006.884486

Cited by 39 publications

(10 citation statements)

References 28 publications

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“…Counterexamples obtained by synchronization diagnostic traces help debugging to decrease the number of synchronization fault candidates. Diagnostic traces can be generated similar to other fault models [13]. In this work we focus only on the synchronization bug model and debugging algorithm without using diagnostic traces.…”

Section: Bug Model-free Sat-based Debuggingmentioning

confidence: 99%

Debug Automation for Synchronization Bugs at RTL

Dehbashi

Fey

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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Abstract-One major concern in the design of Very-LargeScale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bugs due to coding mistakes at RTL. In particular, we introduce an appropriate bug model and show how synchronization bugs are differentiated from other types of bugs by our approach. The experimental results on LGsynth93 and ITC-99 benchmark suites and RTL modules of OpenRISC and OpenSPARC CPUs show diagnosis accuracy and efficiency of the approach.Keywords-debug automation, synchronization bug, SAT-based debugging I. INTRODUCTION Due to the increasing design size and complexity of VLSI circuits, the cost of VLSI systems verification and debugging has significantly increased. Verification tools check the correctness of a design against its specification. Upon detection of a design error, the error is returned as a counterexample. Having a counterexample, the debug process starts localizing and rectifying the bug. But this process is often a manual task which needs a large effort. Thus, automated approaches to design debugging are necessary to decrease the development cycle of VLSI products.Design bugs at RTL are classified into three major classes: logic bugs, algorithmic bugs and synchronization bugs . Algorithmic bugs can have a severe impact on the correctness of a design and they usually require multiple major modifications to be fixed. Synchronization bugs are related to synchronization of data with respect to clock cycles in a design. For most of the synchronization bugs, a signal requires to be latched a cycle earlier or a cycle later in order to keep the correct timing behavior of signals in the design [1]. The most common fix for this class of design bugs is the manual addition or removal of flipflops to satisfy the correct timing behavior of the circuit. These bug models are called missing flipflop and extra flipflop.In the pre-silicon stage, a design is verified against its specification by verification tools. A specification describes the correct timing behavior of a design. The work in [6] presents a formal method to specify the relations between multiple clocks and to model the possible behaviors. Then, a hardware design is verified against the specified clock constraints. An efficient clock modeling approach is presented in [7] to handle clock related challenges uniformly. The approach converts multiple clocks with arbitrary frequencies and ratios, gated clocks, multiple phases, latches and flip-flops in multi-clock synchronous system, into a single-clock model. Clock constraints are automatically generated to avoid unnecessary unrolling and loop-checks in Bounded Model Checking (BMC).The work in [2] presents a model based on Boolean satisfiability to automate debugging of logic bugs. A circuit is enhanced with correction block in order to find the...

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Section: Bug Model-free Sat-based Debuggingmentioning

confidence: 99%

Debug Automation for Synchronization Bugs at RTL

Dehbashi

Fey

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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“…It is commonly used for diagnostic pattern generation in previous works [15,16,19,20], but the connection method of D 1 and D 2 may be different. In our work, we also construct a kind of miter-circuit.…”

Section: Circuit Transformation and Fault List Creationmentioning

confidence: 99%

“…Previous works [9][10][11][12][13][14][15][16][17][18][19][20] around Automatic Diagnostic Pattern Generation (ADPG) can be classified into two categories: (1) pre-test ADPG [9][10][11][12][13][14][15][16][17] and (2) post-diagnosis ADPG [18][19][20]. In the first category [9][10][11][12][13][14][15][16][17], the diagnostic patterns are generated by modifying, reordering, or supplying new patterns to the original test patterns to achieve high distinguishability.…”

Section: Introductionmentioning

confidence: 99%

“…These patterns are loaded into the Automatic Test Equipment (ATE) for test firstly, and then the failing responses are unloaded for volume diagnosis. In the second category [18][19][20], after the first diagnosis run, to further distinguish the reported candidates, the diagnostic patterns are generated. These patterns are loaded into the ATE to get the failing responses for analysis again.…”

Section: Introductionmentioning

confidence: 99%

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Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

Zhang

et al. 2010

2010 19th IEEE Asian Test Symposium

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1 Volume diagnosis plays an important role in the yield learning process. To get a high quality diagnosis result, patterns with high distinguishability are essential. However, the test patterns used by volume diagnosis commonly have low distinguishability to specific faults. In our experiments, we observe that on average, under automatic generated test patterns, faults in the same fanout free region (FFR) account for only 6% of all possible fault pairs, but their share in total indistinguishable faults is 70%; faults in different FFRs but with the same observation points account for 4% of all fault pairs, but their share in total indistinguishable faults is 22%. Exploiting this fact that faults in the same FFRs are harder to be distinguished, we propose an Automatic Diagnostic Pattern Generation (ADPG) method named Substantial Fault Pairs at-A-Time (SFPAT)-ADPG. By applying a transformed circuit and a new fault list to an existing Automatic Test Pattern Generation (ATPG) tool, we generate the compressed test patterns which are also the diagnostic patterns with high distinguishability for the original circuit. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed SFPAT-ADPG method.

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“…Therefore, in more than 60% of the cases where a chip is returned for defect analysis, multiple fault diagnosis is required and the classical single stuck-at fault model may be inadequate (Huisman, 2004). The main difficulty in multiple fault simulation is in handling a very large number of multiple faults (Lin et al, 2007). The order of multiple faults in a circuit with 'n' nodes is 3 n -1 as compared to 2n single stuck-at faults.…”

Section: Introductionmentioning

confidence: 99%

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Anita

Sudheesh

2016

IJHPSA

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An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing.

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Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation

Cited by 39 publications

References 28 publications

Debug Automation for Synchronization Bugs at RTL

Debug Automation for Synchronization Bugs at RTL

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

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