2024
DOI: 10.21203/rs.3.rs-3850786/v1
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Multiple Fault Tolerant PUC Multilevel Inverter Using the Concept of Redundancy with Low Total Blocking Voltage, Device Count and High Post-Fault Efficiency for Five Switches Fault

Hillol Phukan,
Dinesh Kumar Tiwari,
Jiwanjot Singh
et al.

Abstract: In this article, a fault-tolerant Packed U Cell MLI (FT-PUC-MLI) is presented, which utilizes two DC sources with nine main switches and eight redundant switches for creating 7-level across the output. The proposed topology uses phase disposition sinusoidal pulse width modulation (PD-SPWM) for the generation of gate signals. A detailed analysis of the proposed topology is done with respect to efficiency, power loss and total harmonics distortions (THD). A brief comparative analysis in terms of device count, to… Show more

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