Multiple Node Upset-Tolerant Latch Design

Liu, Xin

doi:10.1109/tdmr.2019.2912811

Cited by 34 publications

(21 citation statements)

References 17 publications

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“…Moreover, in highly-integrated nano-scale ICs, due to double-node charge collection [5], a radiative particle can simultaneously change the logic values of two nodes in a storage cell, and thus results in a DNU. The scenario that three nodes are simultaneously impacted is called a TNU [6][7][8][9]. Clearly, design for reliability against SNUs and/or SETs only are no longer sufficient for safety-critical applications.…”

Section: Introductionmentioning

confidence: 99%

“…Xiaoqing Wen is with the Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka 820-8502, Japan (E-mail: wen@cse.kyutech.ac.jp) have proposed many circuit components such as static random access memories (SRAMs) [10][11][12][13], flip-flops [14][15][16][17], and latches [6][7][8][9][18][19][20][21][22][23][24][25][26][27][28]. Note that this paper proposes two contributions, i.e., voter designs and latch hardening.…”

Section: Introductionmentioning

confidence: 99%

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Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

Yan

Fan

Liang

et al. 2022

IEEE Trans. Aerosp. Electron. Syst.

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With the reduction of technology nodes now reaching 2nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), singleevent-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This paper first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this paper also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2%, 32.8%, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called HITTSFL latch can reduce delay, power, and area by 78.9%, 15.8%, and 28.6%, respectively, compared with the state-ofthe-art TNU hardened latch (TNUHL).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

Yan

Fan

Liang

et al. 2022

IEEE Trans. Aerosp. Electron. Syst.

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show abstract

“…However, in the advanced highly-integrated nano-scale CMOS technologies, due to charge-sharing, a high-energy striking-particle can unfortunately simultaneously change the logic states of double nodes in a storage cell, resulting in a DNU. The scenario that triple nodes are simultaneously affected is called a TNU [4][5][6][7][8]. Obviously, reliability design against soft errors only targeting SNUs and/or SETs are no longer sufficient for high reliability requirements in safety-critical applications.…”

Section: Introductionmentioning

confidence: 99%

“…To mitigate SNUs, DNUs, TNUs, and/or SETs, by means of radiation-hardening-by-design (RHBD) approaches, many hardened storage cells such as static random access memories (SRAMs) [9][10][11][12], flip-flops [13][14][15][16], and latches [5][6][7][8][17][18][19][20][21][22][23][24][25][26][27], have been proposed. This paper focuses on latches.…”

Section: Introductionmentioning

confidence: 99%

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Yan

Feng

Zhao

et al. 2020

2020 57th ACM/IEEE Design Automation Conference (DAC)

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This paper proposes a cost-effective, high-impedancestate (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storagecells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-theart TNU hardened latch (TNUHL) that cannot filter SETs.

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“…To evade these radiation effects, many hardened by design techniques have been proposed to deal with Single Event Transients (SETs), SEUs and Multiple Event Transients (METs) [5]- [21]. The advantages of these methods are that they are highly resistant to SETs and SEUs.…”

Section: Introductionmentioning

confidence: 99%

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

Kumar

Kumaravel

2019

IJACSA

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CMOS based circuits are more susceptible to the radiation environment as the critical charge (Q crit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 µA.

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Multiple Node Upset-Tolerant Latch Design

Cited by 34 publications

References 17 publications

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

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